公开(公告)号：US10977198B2

公开(公告)日：2021-04-13

申请号：US16128882

申请日：2018-09-12

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Marco Dallabora ,  Daniele Balluchi ,  Paolo Amato ,  Luca Porzio

IPC: G06F13/16 ,  G06F13/28

Abstract: The present disclosure includes apparatuses and methods related to a hybrid memory system interface. An example computing system includes a processing resource and a storage system coupled to the processing resource via a hybrid interface. The hybrid interface can provide an input/output (I/O) access path to the storage system that supports both block level storage I/O access requests and sub-block level storage I/O access requests.

公开(公告)号：US10705747B2

公开(公告)日：2020-07-07

申请号：US15927339

申请日：2018-03-21

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Dallabora ,  Roberto Izzi ,  Paolo Amato ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F3/06

Abstract: An example apparatus includes a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to assign a sensitivity to a command and cause the command to be selectively diverted to the hybrid memory system based, at least in part, on the assigned sensitivity.

公开(公告)号：US10585625B2

公开(公告)日：2020-03-10

申请号：US16033430

申请日：2018-07-12

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Paolo Amato

IPC: G06F3/06 ,  G06F11/07

Abstract: An apparatus can have an array of memory cells and a controller coupled to the array. The controller can be configured to read a group sentinel cells of the array and without reading a number of other groups of cells of the array to determine that data stored in the number of other groups of cells lacks integrity based on a determination that data stored in the group of sentinel cells lacks integrity.

公开(公告)号：US20200019342A1

公开(公告)日：2020-01-16

申请号：US16033430

申请日：2018-07-12

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Paolo Amato

IPC: G06F3/06 ,  G06F11/07

Abstract: An apparatus can have an array of memory cells and a controller coupled to the array. The controller can be configured to read a group sentinel cells of the array and without reading a number of other groups of cells of the array to determine that data stored in the number of other groups of cells lacks integrity based on a determination that data stored in the group of sentinel cells lacks integrity.

公开(公告)号：US10529428B2

公开(公告)日：2020-01-07

申请号：US16388501

申请日：2019-04-18

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Corrado Villa

IPC: G11C7/00 ,  G11C16/10 ,  G11C13/00 ,  G11C8/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34 ,  G11C16/08 ,  G11C16/04

Abstract: The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array.

公开(公告)号：US20190370166A1

公开(公告)日：2019-12-05

申请号：US15994477

申请日：2018-05-31

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Daniele Balluchi

IPC: G06F12/02 ,  G06F3/06 ,  G11C16/34 ,  G06F1/32

Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in memory having two portions of data. An embodiment includes a memory having a plurality of physical blocks of memory cells, and a first and second portion of data having a first and second, respectively, number of logical block addresses associated therewith. Two of the plurality of physical blocks of cells do not have data stored therein. Circuitry is configured to relocate the data of the first portion that is associated with one of the first number of logical block addresses to one of the two physical blocks of cells that don't have data stored therein, and relocate the data of the second portion that is associated with one of the second number of logical block addresses to the other one of the two physical blocks of cells that don't have data stored therein.

公开(公告)号：US20190324672A1

公开(公告)日：2019-10-24

申请号：US15958614

申请日：2018-04-20

Applicant: Micron Technology, Inc.

Inventor： Robert N. Hasbun ,  Daniele Balluchi

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods for counter update operations. An example apparatus comprises a memory including a managed unit that includes a plurality of first groups of memory cells and a second group of memory cells, in which respective counters associated with the managed unit are stored on the second group of memory cells. The example apparatus further includes a controller. The controller includes a core configured to route a memory operation request received from a host and a datapath coupled to the core and the memory. The datapath may be configured to issue, responsive to a receipt of the memory operation request routed from the core, a plurality of commands associated with the routed memory operation request to the memory to perform corresponding memory operations on the plurality of first groups of memory cells. The respective counters may be updated independently of the plurality of commands.

公开(公告)号：US10261876B2

公开(公告)日：2019-04-16

申请号：US15345862

申请日：2016-11-08

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Emanuele Confalonieri ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio

IPC: G06F11/20 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.

公开(公告)号：US20190035470A1

公开(公告)日：2019-01-31

申请号：US16059775

申请日：2018-08-09

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Corrado Villa

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C13/00 ,  G11C8/08

Abstract: The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array.

公开(公告)号：US10146477B2

公开(公告)日：2018-12-04

申请号：US15246735

申请日：2016-08-25

Applicant: Micron Technology, Inc.

Inventor： Victor Y. Tsai ,  Danilo Caraccio ,  Daniele Balluchi ,  Neal A. Galbo ,  Robert Warren

IPC: G06F3/06

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.