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公开(公告)号：US11183267B2
公开(公告)日：2021-11-23
申请号：US16510778
申请日：2019-07-12
Applicant: Micron Technology, Inc.
Inventor： Jian Huang , Zhenming Zhou
Abstract: A system includes a memory component, and a processing device coupled with the memory component. The processing device to identify a group of management units of the memory component, wherein the group of management units is included in a set of retired groups of management units, select a management unit from the group of management units, perform a media integrity check on the management unit to determine a failed bit count of the management unit, and in response to the failed bit count of the management unit failing to satisfy a threshold criterion, remove the group of management units from the set of retired groups of management units.
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公开(公告)号：US12224017B2
公开(公告)日：2025-02-11
申请号：US17942977
申请日：2022-09-12
Applicant: Micron Technology, Inc.
Inventor： Nagendra Prasad Ganesh Rao , Paing Z. Htet , Sead Zildzic, Jr. , Thomas Fiala , Jian Huang , Zhenming Zhou
Abstract: A system can include a memory device containing blocks made up of wordlines respectively connected to sets of memory cells, and a processing device, operatively coupled with the memory device to perform operations including responsive to receiving a read request that specifies a block, determining a value of a metric reflective of a number of programmed wordlines of the block. The operations can also include responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric, and performing, using the read voltage offset, a read operation responsive to the read request.
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公开(公告)号：US12210752B2
公开(公告)日：2025-01-28
申请号：US18372998
申请日：2023-09-26
Applicant: Micron Technology, Inc.
Inventor： Zhongguang Xu , Jian Huang , Tingjun Xie , Murong Lang , Zhenming Zhou
IPC: G06F3/06
Abstract: A request to perform a memory access operation on a plurality of memory cells of a memory device is received. In response to determining that the request is from a host, a first error recovery operation is performed, wherein the first error recovery operation is associated with a first plurality of demarcation voltages. In response to determining that the request is from a controller, a second error recovery operation is performed, wherein the second error recovery operation is associated with a second plurality of demarcation voltages, wherein the second plurality of demarcation voltages comprises a greater number of demarcation voltages than the first plurality of demarcation voltages.
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公开(公告)号：US12176060B2
公开(公告)日：2024-12-24
申请号：US18531003
申请日：2023-12-06
Applicant: Micron Technology, Inc.
Inventor： Murong Lang , Zhenming Zhou , Jian Huang , Zhongguang Xu , Jiangli Zhu
IPC: G11C7/10
Abstract: A read operation is performed on a set of memory cells addressable by a first wordline (WL), wherein the set of memory cells is comprised by an open translation unit (TU_of memory cells of a memory device. Respective threshold voltage offset bins for each WL of a second plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on a threshold voltage offset bin associated with the first WL. Respective default threshold voltages for each WL of the first plurality of WLs are updated based on the respective threshold voltage offset bins for each WL of the second plurality of WLs.
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公开(公告)号：US20240105240A1
公开(公告)日：2024-03-28
申请号：US18531003
申请日：2023-12-06
Applicant: Micron Technology, Inc.
Inventor： Murong Lang , Zhenming Zhou , Jian Huang , Zhongguang Xu , Jiangli Zhu
IPC: G11C7/10
CPC classification number: G11C7/1063
Abstract: A read operation is performed on a set of memory cells addressable by a first wordline (WL), wherein the set of memory cells is comprised by an open translation unit (TU_of memory cells of a memory device. Respective threshold voltage offset bins for each WL of a second plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on a threshold voltage offset bin associated with the first WL. Respective default threshold voltages for each WL of the first plurality of WLs are updated based on the respective threshold voltage offset bins for each WL of the second plurality of WLs.
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Patent Agency Ranking
公开(公告)号：US20240020025A1
公开(公告)日：2024-01-18
申请号：US18372998
申请日：2023-09-26
Applicant: Micron Technology, Inc.
Inventor： Zhongguang Xu , Jian Huang , Tingjun Xie , Murong Lang , Zhenming Zhou
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0679 , G06F3/0655
Abstract: A request to perform a memory access operation on a plurality of memory cells of a memory device is received. In response to determining that the request is from a host, a first error recovery operation is performed, wherein the first error recovery operation is associated with a first plurality of demarcation voltages. In response to determining that the request is from a controller, a second error recovery operation is performed, wherein the second error recovery operation is associated with a second plurality of demarcation voltages, wherein the second plurality of demarcation voltages comprises a greater number of demarcation voltages than the first plurality of demarcation voltages.
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公开(公告)号：US11734190B2
公开(公告)日：2023-08-22
申请号：US17319497
申请日：2021-05-13
Applicant: Micron Technology, Inc.
Inventor： Jian Huang , Zhenming Zhou
IPC: G06F11/30 , G06F12/1009 , G06F11/10 , G06F12/04
CPC classification number: G06F12/1009 , G06F11/1068 , G06F12/04 , G06F2212/657
Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, selecting, by the processing device, a first partition located on a first die of the memory device. The operations performed by the processing device further include selecting, based on a predefined partition offset reflecting a physical layout of the memory device, a second partition located on a second die of the memory device. The operations performed by the processing device further include generating a codeword comprising first data residing on the first partition and second data residing on the second partition.
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28.发明申请公开(公告)号：US20230027144A1
公开(公告)日：2023-01-26
申请号：US17958920
申请日：2022-10-03
Applicant: Micron Technology, Inc.
Inventor： Zhenming Zhou , Jian Huang , Jiangli Zhu
Abstract: An error associated with a read operation corresponding to a memory die of a memory subsystem is detected. In response to detecting the error, a first read throughput level of the memory subsystem is identified. A quantity of queues receiving operation requests is decreased, the decreased quantity of queues corresponding to a second read throughput level. A read retry operation associated with the memory die is initiated at the second read throughput level.
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公开(公告)号：US20250124987A1
公开(公告)日：2025-04-17
申请号：US18990013
申请日：2024-12-20
Applicant: Micron Technology, Inc.
Inventor： Nagendra Prasad Ganesh Rao , Paing Z. Htet , Sead Zildzic, JR. , Thomas Fiala , Jian Huang , Zhenming Zhou
Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations, including: determining a read voltage offset corresponding to a value of a metric reflective of a programmed state of a set of memory cells of the memory device; and performing, using the read voltage offset, a memory access operation with respect to the set of memory cells.
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公开(公告)号：US20240347110A1
公开(公告)日：2024-10-17
申请号：US18755062
申请日：2024-06-26
Applicant: Micron Technology, Inc.
Inventor： Jian Huang , Zhenming Zhou
CPC classification number: G11C16/102 , G11C16/08 , G11C16/26 , G11C29/4401 , G11C2029/1202
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a write operation to program first data to a first set of memory cells addressable by a first wordline of a first plurality of wordlines of a block of the memory device; performing a read operation on a second wordline of the plurality of wordlines, wherein the second wordline is adjacent to the first wordline; determining a number of bits programmed in a first logical level in the second wordline; and responsive to determining that the number of bits programmed in the first logical level fails to satisfy a threshold criterion, performing a write operation on the second wordline to program second data.
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