公开(公告)号：US11901014B2

公开(公告)日：2024-02-13

申请号：US17739741

申请日：2022-05-09

Applicant: Micron Technology, Inc.

Inventor： Zhongguang Xu ,  Nicola Ciocchini ,  Zhenlei Shen ,  Charles See Yeung Kwong ,  Murong Lang ,  Ugo Russo ,  Niccolo' Righetti

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3481

Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.

公开(公告)号：US20230395156A1

公开(公告)日：2023-12-07

申请号：US17831350

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Zhongyuan Lu ,  Niccolo' Righetti

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/08 ,  G11C7/04

CPC classification number: G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/08 ,  G11C7/04

Abstract: Bake temperatures for memory blocks can be determined as part of an operation to allocate memory blocks for us by a memory device. If a temperature of a particular memory block among the plurality of memory blocks meets or exceeds a threshold operational temperature corresponding to a memory device containing the plurality of memory blocks, the particular memory block can be allocated for receipt and/or storage of data.

公开(公告)号：US20230360704A1

公开(公告)日：2023-11-09

申请号：US17739741

申请日：2022-05-09

Applicant: Micron Technology, Inc.

Inventor： Zhongguang Xu ,  Nicola Ciocchini ,  Zhenlei Shen ,  Charles See Yeung Kwong ,  Murong Lang ,  Ugo Russo ,  Niccolo' Righetti

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3481

Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.

公开(公告)号：US20230044883A1

公开(公告)日：2023-02-09

申请号：US17971346

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, JR. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory component comprises a cyclic buffer partition portion and a snapshot partition portion. In response to receiving a signal that a trigger event has occurred, a processing device included in the memory component performs an error correction operation on a portion of data stored in the cyclic buffer partition portion, copies the data stored in the cyclic buffer partition portion to the snapshot partition portion in response to the error correction operation being successful, and sends the data stored in the cyclic buffer partition portion to a processing device operatively coupled to the memory component in response to the error correction operation not being successful.

公开(公告)号：US20220350517A1

公开(公告)日：2022-11-03

申请号：US17846462

申请日：2022-06-22

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, JR. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F3/06

Abstract: A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.

公开(公告)号：US11461035B2

公开(公告)日：2022-10-04

申请号：US17127373

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Priya Venkataraman ,  Pitamber Shukla ,  Scott A. Stoller ,  Giuseppina Puzzilli ,  Niccolo' Righetti

IPC: G06F3/06

Abstract: A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.

公开(公告)号：US20220199163A1

公开(公告)日：2022-06-23

申请号：US17127358

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Scott A. Stoller ,  Pitamber Shukla ,  Priya Venkataraman ,  Giuseppina Puzzilli ,  Niccolo' Righetti

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/34

Abstract: A method is described that includes performing a first erase operation on a set of memory cells of a memory device using an erase voltage, which is set to a first voltage value and adjusting the erase voltage to a second voltage value based on feedback from performance of at least the first erase operation. The method further includes performing a second erase operation on the set of memory cells using the erase voltage, which is set to the second voltage value. In this configuration, the erase voltage set to the second voltage value is an initial voltage applied to the set of memory cells to perform erase operations such that each subsequent erase operation on the set of memory cells following the first erase operation uses an erase voltage that is equal to or greater than the second voltage value when erasing the first set of memory cells.

公开(公告)号：US11360700B2

公开(公告)日：2022-06-14

申请号：US16995645

申请日：2020-08-17

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F3/06 ,  G06F1/26

Abstract: A system includes a processing device and a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion and a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can further include a first sub-partition portion having a first programming characteristic and a second sub-partition portion having a second programming characteristic. The processing device can write received data sequentially to the cycle buffer partition portion and write, based at least in part on a determination that a trigger event has occurred, data from the cyclic buffer partition portion to the first sub-partition portion or the second sub-partition portion, or both.

公开(公告)号：US20220068407A1

公开(公告)日：2022-03-03

申请号：US17001757

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Giuseppina Puzzilli ,  Karl D. Schuh ,  Jeffrey S. McNeil, JR. ,  Kishore K. Muchherla ,  Ashutosh Malshe ,  Niccolo' Righetti

IPC: G11C16/34 ,  G11C16/04

Abstract: A change in a read window of a group of memory cells of a memory device that has undergone a plurality of program/erase cycles (PECs) can be determined. read voltage can be determined based at least in part on the determined change in the read window.

公开(公告)号：US20250014655A1

公开(公告)日：2025-01-09

申请号：US18895236

申请日：2024-09-24

Applicant: Micron Technology, Inc.

Inventor： Nicola Ciocchini ,  Animesh R. Chowdhury ,  Kishore Kumar Muchherla ,  Akira Goda ,  Jung Sheng Hoei ,  Niccolo' Righetti ,  Jonathan S. Parry

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/26

Abstract: Methods, systems, and apparatuses include receiving a read command including a logical address. The read command is directed to a portion of memory composed of blocks and each block is composed of wordline groups. The physical address for the read command is identified using the logical address. The wordline group is determined using the physical address. A slope factor is retrieved using the wordline group. A read counter is incremented using the slope factor.