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    ADDRESS VERIFICATION AT A MEMORY SYSTEM
    21.
    发明申请
    ADDRESS VERIFICATION AT A MEMORY SYSTEM 有权

    公开(公告)号：US20250103245A1

    公开(公告)日：2025-03-27

    申请号：US18912322

    申请日：2024-10-10

    Applicant: Micron Technology, Inc.

    Inventor： Stephen Hanna

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for address verification at a memory system are described. A memory system may determine an address identifier based on a received read command and maintain the determined address identifier in a protected state to validate a subsequent read operation. For example, the memory system may store the determined address identifier in a first memory array, separate from a second memory array that is read from in response to the read command. The memory system may also extract an address identifier from memory cells being read in response to the read command, which may include decoding or other interpreting operations performed on information read from the memory cells. The address identifier extracted from the memory cells may be compared with the address identifier determined from the read command and maintained in the protected state, which may support a determination of how to respond to the read command.

    Address verification at a memory system
    22.
    发明授权
    Address verification at a memory system 有权

    公开(公告)号：US12124738B2

    公开(公告)日：2024-10-22

    申请号：US17883191

    申请日：2022-08-08

    Applicant: Micron Technology, Inc.

    Inventor： Stephen Hanna

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619

    Abstract: Methods, systems, and devices for address verification at a memory system are described. A memory system may determine an address identifier based on a received read command and maintain the determined address identifier in a protected state to validate a subsequent read operation. For example, the memory system may store the determined address identifier in a first memory array, separate from a second memory array that is read from in response to the read command. The memory system may also extract an address identifier from memory cells being read in response to the read command, which may include decoding or other interpreting operations performed on information read from the memory cells. The address identifier extracted from the memory cells may be compared with the address identifier determined from the read command and maintained in the protected state, which may support a determination of how to respond to the read command.

    CREATING HIGH DENSITY LOGICAL TO PHYSICAL MAPPING
    23.
    发明公开
    CREATING HIGH DENSITY LOGICAL TO PHYSICAL MAPPING 审中-公开

    公开(公告)号：US20240289279A1

    公开(公告)日：2024-08-29

    申请号：US18598978

    申请日：2024-03-07

    Applicant: Micron Technology, Inc.

    Inventor： Stephen Hanna

    IPC: G06F12/1009 ,  G06F12/02

    CPC classification number: G06F12/1009 ,  G06F12/0246 ,  G06F2212/7201

    Abstract: Methods, systems, and devices for creating high density logical to physical mapping are described. A memory system may implement storage of mapping information to store the logical addresses and the corresponding physical addresses. A memory system may receive a command associated with data and a corresponding set of logical addresses, and in some cases the memory device may determine that the logical addresses are sequential. The memory device may generate and store a set of compressed entries in a macro level of the mapping information. When the memory system receives a command associated with an exception to the sequential logical addresses, the memory system may update an entry of the macro level to include a pointer to a set of entries in another level of the mapping information.

    DEVICE RESET ALERT MECHANISM
    26.
    发明公开
    DEVICE RESET ALERT MECHANISM 审中-公开

    公开(公告)号：US20230267047A1

    公开(公告)日：2023-08-24

    申请号：US17738645

    申请日：2022-05-06

    Applicant: Micron Technology, Inc.

    Inventor： Stephen Hanna

    IPC: G06F11/14

    CPC classification number: G06F11/1441 ,  G06F2201/805

    Abstract: Methods, systems, and devices for device reset alert mechanism are described. The memory system may identify a fault condition associated with resetting the memory system and set, in a register associated with event alerts of the memory system, a first indication for a reset of the memory system. In some cases, the memory system may transmit a message that includes a second indication that the register associated with event alerts of the memory system has been changed based on setting the register. The memory system may reset one or more components of the memory system based on the first indication and the second indication

    FACILITATING SEQUENTIAL READS IN MEMORY SUB-SYSTEMS
    28.
    发明申请
    FACILITATING SEQUENTIAL READS IN MEMORY SUB-SYSTEMS 有权

    公开(公告)号：US20210263864A1

    公开(公告)日：2021-08-26

    申请号：US16801949

    申请日：2020-02-26

    Applicant: Micron Technology, Inc.

    Inventor： Stephen Hanna ,  Nadav Grosz

    IPC: G06F12/14 ,  G06F12/02 ,  G06F12/06 ,  G06F1/24 ,  G06F21/79

    Abstract: An example memory subsystem includes a memory component and a processing device, operatively coupled to the memory component. The processing device is configured to receive a plurality of logical-to-physical (L2P) records, wherein an L2P record of the plurality of L2P records maps a logical block address to a physical address of a memory block on the memory component; determine a sequential assist value specifying a number of logical block addresses that are mapped to consecutive physical addresses sequentially following the physical address specified by the L2P record; generate a security token encoding the sequential assist value; and associate the security token with the L2P record.

    ELECTRICAL DEVICE WITH TEST INTERFACE
    29.
    发明申请
    ELECTRICAL DEVICE WITH TEST INTERFACE 有权

    公开(公告)号：US20210142861A1

    公开(公告)日：2021-05-13

    申请号：US17152352

    申请日：2021-01-19

    Applicant: Micron Technology, Inc.

    Inventor： Stephen Hanna

    IPC: G11C29/48 ,  G06F13/16

    Abstract: An example system comprises: a master bus electrically coupled to a master multiplexer controlled by a test mode signal selecting between a master physical interface (PHY) and a slave bus of a plurality of slave buses, wherein each slave bus is electrically coupled to a respective slave multiplexer selecting between a respective slave PHY and the master bus; a plurality of electrical circuits, wherein each electrical circuit of the plurality of electrical circuits is electrically coupled to one of: the master bus or a slave bus of the plurality of slave buses; and a memory test interface electrically coupled to the master bus.

    Creating high density logical to physical mapping
    30.
    发明授权
    Creating high density logical to physical mapping 有权

    公开(公告)号：US12271317B2

    公开(公告)日：2025-04-08

    申请号：US18598978

    申请日：2024-03-07

    Applicant: Micron Technology, Inc.

    Inventor： Stephen Hanna

    IPC: G06F12/10 ,  G06F12/02 ,  G06F12/1009

    Abstract: Methods, systems, and devices for creating high density logical to physical mapping are described. A memory system may implement storage of mapping information to store the logical addresses and the corresponding physical addresses. A memory system may receive a command associated with data and a corresponding set of logical addresses, and in some cases the memory device may determine that the logical addresses are sequential. The memory device may generate and store a set of compressed entries in a macro level of the mapping information. When the memory system receives a command associated with an exception to the sequential logical addresses, the memory system may update an entry of the macro level to include a pointer to a set of entries in another level of the mapping information.

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