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公开(公告)号：US20250156087A1
公开(公告)日：2025-05-15
申请号：US19025934
申请日：2025-01-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sujeet Ayyapureddi
Abstract: Apparatuses, systems, and methods for managing access to metadata stored at a memory. To manage access to metadata, a mode register is configured to receive a metadata enable setting and to provide a metadata enable signal based on the metadata enable setting. A metadata access control circuit configured to receive a column address identifying a particular column to be accessed within a memory array. The metadata access control circuit blocks access to a column corresponding to the column address when the column address matches one of a plurality of particular column addresses designated for storage of metadata and the metadata enable signal has a first value, and permits access to a column corresponding to the column address when the column address is different than every one of the a plurality of particular column addresses designated for storage of metadata or the metadata enable signal has a second value.
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公开(公告)号：US20250130897A1
公开(公告)日：2025-04-24
申请号：US18789201
申请日：2024-07-30
Applicant: Micron Technology, Inc.
Inventor： Sujeet Ayyapureddi
IPC: G06F11/10
Abstract: Methods, systems, and apparatuses for a memory device (e.g., DRAM) including a directed error check and scrub (ECS) procedure are described. The directed ECS procedure may include read-modify-write cycles when errors are detected in code words. In some embodiments, the memory device may perform the directed ECS procedure on a code word in which an error was previously detected (for example, in response to a read command). The directed ECS procedure described herein may facilitate correcting code word errors before too many errors, exceeding the detection and/or correction capabilities of the memory device, accumulate in the code words.
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公开(公告)号：US20250111887A1
公开(公告)日：2025-04-03
申请号：US18747712
申请日：2024-06-19
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sujeet Ayyapureddi
Abstract: Apparatuses, systems, and methods for separate write enable signals for granular single pass metadata access operations. During an example write operation a memory may receive data bits and at least one metadata bit. A set of bit lines in a first column plane is selected and a first write enable signal is provided which enables writing data to each of that set of bit lines. A second set of bit lines in a second column plane is selected and a second write enable signal is provided which enables writing the at least one metadata bit to a selected subset of the second set of bit lines.
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公开(公告)号：US20250110830A1
公开(公告)日：2025-04-03
申请号：US18747676
申请日：2024-06-19
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sujeet Ayyapureddi
Abstract: Apparatuses, systems, and methods for alternate memory die metadata storage. A memory module includes a number of memory devices. A controller writes data and metadata to the module. The data is stored in the memory devices, while the metadata is stored in a selected portion of the memory devices. The selected portion of the memory devices may use separate write enable signals to protect bit lines which the metadata is not being written to.
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公开(公告)号：US12260896B2
公开(公告)日：2025-03-25
申请号：US17965706
申请日：2022-10-13
Applicant: Micron Technology, Inc.
Inventor： Sujeet Ayyapureddi
IPC: G11C11/4078 , G11C5/00 , G11C11/4096 , G11C29/52 , G11C7/24 , G11C8/08 , G11C29/04
Abstract: Methods, apparatuses, and systems related to operations for memory process feedback. A controller can monitor memory activities, such as processes, identify row hammer aggressors, and perform mitigating steps to the row hammer aggressors. The controller may have a table of addresses of row hammer aggressors and perform operations of tracking row hammer aggressors. The controller can determine whether the number of aggressors reaches a threshold. When the number of aggressors reaches the threshold, the controller can send a message with the aggressor addresses to the operating system. The operating system can perform mitigating steps to the row hammer aggressors. In some embodiments, the controller may identify the row hammer aggressors and inject poisoned data into the process to mitigate the row hammer aggressors.
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Patent Agency Ranking
公开(公告)号：US20250078950A1
公开(公告)日：2025-03-06
申请号：US18745894
申请日：2024-06-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sujeet Ayyapureddi
IPC: G11C29/52 , G11C11/408 , G11C11/4096
Abstract: Apparatuses, systems, and methods for half-page modes. A memory device may be operated in a full-page mode where all the memory cells along a word line are used for data or a half-page mode where less than all of the memory cells are used for data. In some memory devices, each half of the memory cells may be separately activated by different word line portions. In some half-page modes, data may be stored along a selected portion of the memory cells and additional information such as metadata or module parity may be stored along the non-selected portion of the memory cells. The additional information may be provided along additional data terminals so as not to increase the data burst length.
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公开(公告)号：US20250078904A1
公开(公告)日：2025-03-06
申请号：US18789344
申请日：2024-07-30
Applicant: Micron Technology, Inc.
Inventor： Sujeet Ayyapureddi
IPC: G11C11/4078 , G11C11/406
Abstract: Disclosed are methods, systems, and apparatuses for providing per-channel row hammer alerts, from a memory device to a host, without the use of a dedicated per-channel alert interface. When detecting a row hammer alert condition, the memory device may determine whether an existing interface (e.g., a severity interface used to transmit severity information) is available. The interface may be available outside of certain designated burst positions during a read burst. Once the interface is available, the memory device may transmit a row hammer alert indication to the host. The host may determine whether information received over the interface is associated with a row hammer alert or severity, depending on when the information was received (e.g., in what burst position during a read burst).
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公开(公告)号：US20250031088A1
公开(公告)日：2025-01-23
申请号：US18767732
申请日：2024-07-09
Applicant: Micron Technology, Inc.
Inventor： Sujeet Ayyapureddi
Abstract: Systems and methods for determining a number of data sources for a dynamic ad hoc network are disclosed including receiving information about a vehicle, dynamically adjusting a size of the dynamic ad hoc network for the vehicle based on the received information, receiving navigation or safety information from one or more other vehicles in the dynamic ad hoc network, and determining one or more control inputs to the vehicle based at least in part on the received navigation or safety information from one or more other vehicles in the dynamic ad hoc network.
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公开(公告)号：US20240321328A1
公开(公告)日：2024-09-26
申请号：US18734189
申请日：2024-06-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sujeet Ayyapureddi
CPC classification number: G11C7/1039 , G06F12/06 , G11C7/1012 , G11C7/1048 , G11C7/1069 , G11C7/1096
Abstract: Apparatuses, systems, and methods for managing storage and retrieval of metadata at a memory. A metadata column address generator, during a metadata access operation, is configured to decode a subset of less than all of the bits of the column address to determine a metadata column address and a metadata column plane address corresponding to a particular one of column planes of a memory array. A column decoder is configured to facilitate a double cycle access operation to write data to or retrieve data from the plurality of column planes based on the column address and to write metadata to or retrieve metadata from a particular column corresponding to the metadata column address of the particular one of the column planes corresponding to the column plane address.
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公开(公告)号：US20240311231A1
公开(公告)日：2024-09-19
申请号：US18525395
申请日：2023-11-30
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sujeet Ayyapureddi , Wesley W. Borie , Dennis G. Montierth , Garth N. Grubb , Mow Yiak Goh , Anthony M. Geidl
CPC classification number: G06F11/10 , G06F12/0292 , G06F2212/1032
Abstract: An exemplary host includes a data mapping decoder configured to decode a swizzle mapping signal received from a memory module to provide a data mapping setting, a data input/output circuit configured to receive a plurality of data bits from the memory module via a data bus, and a data adjustment circuit configured to re-arrange an order of the plurality of data bits based on the data mapping setting to provide a plurality of adjusted data bits.
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