公开(公告)号：US10347322B1

公开(公告)日：2019-07-09

申请号：US15900403

申请日：2018-02-20

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Sangmin Hwang ,  Si-Woo Lee

IPC: G11C11/4091 ,  G11C11/4097 ,  G11C11/22

Abstract: Some embodiments include an apparatus having first and second comparative bitlines extending horizontally and coupled with a sense amplifier. First memory cell structures are coupled with the first comparative bitline. Each of the first memory cell structures has a first transistor associated with a first capacitor. Second memory cell structures are coupled with the second comparative bitline. Each of the second memory cell structures has a second transistor associated with a second capacitor. Each of the first capacitors has a container-shaped first node and is vertically offset from an associated first sister capacitor which is a mirror image of its associated first capacitor along a horizontal plane. Each of the second capacitors has a container-shaped first node and is vertically offset from an associated second sister capacitor which is a mirror image of its associated second capacitor along the horizontal plane.

公开(公告)号：US20190019544A1

公开(公告)日：2019-01-17

申请号：US16035147

申请日：2018-07-13

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls ,  Tae H. Kim

IPC: G11C11/22

Abstract: Some memory circuitry comprises a stack of multiple tiers individually comprising memory cells individually comprising an elevationally-extending transistor. The tiers individually comprise multiple access lines that individually electrically couple together a row of the memory cells in that individual tier. The tiers individually comprise access-line-driver circuitry comprising an elevationally-extending transistor.

公开(公告)号：US20180308530A1

公开(公告)日：2018-10-25

申请号：US15495401

申请日：2017-04-24

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim

IPC: G11C7/12 ,  G11C8/10

CPC classification number: G11C8/10 ,  G11C8/08 ,  G11C8/14

Abstract: Methods and apparatuses of providing word line voltages are disclosed. An example method includes: activating and deactivating a word line. Activating the word line includes: rendering the first, second and third transistors conductive, non-conductive and non-conductive, respectively, wherein the first transistor is rendered conductive by supplying a gate of the first transistor with a first voltage; and supplying the first node with an active voltage. Deactivating the word line includes: changing a voltage of the first node from the active voltage to an inactive voltage; changing a voltage of the gate of the first transistor from the first voltage to a second voltage, wherein the first transistor is kept conductive by the second voltage; rendering the third transistor conductive during the gate of the first transistor being at the second voltage; and rendering the first and second transistors non-conductive and conductive, respectively, after the third transistor has been rendered conductive.

公开(公告)号：US20140313810A1

公开(公告)日：2014-10-23

申请号：US13866693

申请日：2013-04-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sangmin Hwang ,  Tae H. Kim ,  Hoyoung Kang

IPC: G11C11/401 ,  G11C11/408

CPC classification number: G11C11/408 ,  G11C7/18 ,  G11C11/4097

Abstract: A memory array includes segmented global and local digit lines in which the global digit line segments are switchably coupled to one of a plurality of local digit line segments at a time. A sense circuit coupled to a global digit line segment can be switched to sense memory cells coupled to one of the plurality of local digit lines at a first time and memory cells coupled to a second one of the plurality of local digit lines at a second time. Neither the global digit line segments nor the local digit line segments extend through the entire memory array.

Abstract translation: 存储器阵列包括分段的全局和局部数字线，其中全局数字线段一次可切换地耦合到多个局部数字线段之一。 耦合到全局数字线段的感测电路可以被切换以感测在第一时间耦合到多个本地数字线中的一个的存储器单元，并且在第二时间耦合到多个本地数字线中的第二个的存储器单元 。 全局数字线段和本地数字线段都不会延伸穿过整个存储器阵列。

公开(公告)号：US20240055043A1

公开(公告)日：2024-02-15

申请号：US17886217

申请日：2022-08-11

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim

IPC: G11C11/408

CPC classification number: G11C11/4085

Abstract: A boost circuit is used to provide boosting voltage to a common boost node of a plurality of sub-word line drivers in memory systems and devices. The boost circuit includes a Metal Insulator Metal Capacitor. By using the boost circuit, the plurality of sub-word line drivers are configured to output a certain voltage to local word lines without using high DC generators to generate high voltages (4.2 volts or more). The area of the semiconductor substrate used for fabricating the sub-word line drivers is reduced, and thus reduce the cost or increasing the capacity of the memory devices.

公开(公告)号：US11450377B2

公开(公告)日：2022-09-20

申请号：US16942588

申请日：2020-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tae H. Kim

IPC: G11C11/4091 ,  G11C11/22 ,  G11C11/4094

Abstract: Apparatuses and methods including memory cells, digit lines, and sense amplifiers are described. An example apparatus includes a pair of digit lines including first and second digit lines, a sense amplifier coupled to the pair of digit lines and configured to amplify a voltage difference between the first and second digit lines when activated, and a plurality of memory cells. A memory cell of the plurality of memory cells includes a first node coupled to the first digit line and includes a second node coupled to the second digit line. The memory cell of the plurality of memory cells is configured to store a respective voltage and/or charge at a respective cell node and couple the respective voltage and/or charge to the first node when activated.

公开(公告)号：US11380387B1

公开(公告)日：2022-07-05

申请号：US17209650

申请日：2021-03-23

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Tae H. Kim

IPC: G11C7/00 ,  G11C11/4091 ,  G11C7/10 ,  H01L27/06 ,  H01L27/108

Abstract: A memory device can comprise an arrays of memory cells comprising a plurality of vertically stacked tiers of memory cells, a respective plurality of horizontal access lines coupled to each of the plurality of tiers of memory cells, and a plurality of vertical sense lines coupled to each of the plurality of tiers of memory cells. The array of memory cells can further comprise a plurality of multiplexors each coupled to a respective vertical sense line, wherein each of the plurality of multiplexors includes a first portion and a second portion, the first portion is coupled to the array of memory cells and the second portion is formed on a substrate material. The array of memory cells can further comprise a semiconductor under the array (SuA) circuitry comprising a plurality of sense amplifiers, each sense amplifier coupled to a respective subset of the plurality of multiplexors.

公开(公告)号：US11302381B1

公开(公告)日：2022-04-12

申请号：US17170743

申请日：2021-02-08

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Brenton P. Van Leeuwen

IPC: G11C11/408 ,  G11C11/22

Abstract: Methods, systems, and devices for driving word lines using sub word line drivers are described. A memory array may include a plurality of sub-arrays arranged with gaps in between. Word lines may be arranged across multiple sub-arrays and drive access transistors that are used to selectively access rows (e.g., rows of memory cells) within the sub-arrays. In some examples, signals applied to selection devices driving the word lines may be over-driven for a duration at or near the desired transitions of the word line, and some signals may be driven to a relatively high level for a duration around the high and low transitions of a global row line. Whether a signal is over driven or driven to a relatively high level may depend on the type or types of transistors used in each word line driver.

公开(公告)号：US11270746B2

公开(公告)日：2022-03-08

申请号：US16548242

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim

IPC: G11C8/08 ,  G11C8/14 ,  G11C11/408

Abstract: A word line driver circuit is disclosed. A word line driver circuit may include a circuit configured to generate a clamped voltage based on a first fixed supply voltage and in response to receipt of a first control signal triggering an active mode. The circuitry may further be configured to generate an internal global word line voltage based on the clamped voltage during the active mode. Further, the word line driver circuit may include at least one main word line driver configured to receive the internal global word line voltage and generate a global word line voltage. Additionally, the word line driver circuit may include at least one sub word line driver configured to receive the global word line voltage and generate a word line voltage.

公开(公告)号：US11257538B2

公开(公告)日：2022-02-22

申请号：US16150996

申请日：2018-10-03

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim

IPC: G11C8/08 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/22 ,  G11C11/4074

Abstract: A memory device is provided. The memory device comprises at least one word line driver comprising a first and a second switching device, wherein the word line driver is configured to activate a word line electrically coupled to one or more memory cells included in a memory bank. The memory device additionally comprises a memory bank controller operatively coupled to the at least one word line driver. The memory bank controller is configured to provide a word line power supply (PH) signal, a word line ON control (GR) signal, and a word line OFF control (PHF) signal to the at least one word line driver, and to adjust a timing of the PH, the GR, and the PHF signals to reduce or to eliminate a non-conducting stress (NCS) condition, a time dependent temperature instability (TDDB) condition, or a combination thereof, of the first switching device, of the second switching device, or of a combination thereof.