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    GROUPING POWER SUPPLIES FOR A SLEEP MODE
    21.
    发明申请
    GROUPING POWER SUPPLIES FOR A SLEEP MODE 有权

    公开(公告)号：US20210373648A1

    公开(公告)日：2021-12-02

    申请号：US16890819

    申请日：2020-06-02

    Applicant: Micron Technology, Inc.

    Inventor： Ki-Jun Nam ,  Yantao Ma ,  Yasushi Matsubara ,  Takamasa Suzuki

    IPC: G06F1/3296 ,  G11C11/22 ,  G06F1/3234

    Abstract: Methods, systems, and devices for grouping power supplies for a power saving mode are described to configure a memory device with groups of internal power supplies whose voltage levels may be successively modified according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, respective voltage levels of a first group of internal power supplies may be modified to respective external power supply voltage levels at a first time, respective voltage levels of a second group of internal power supplies may be modified to respective external power supply voltage levels at a second time, and so on. When the memory device exits the deep sleep mode, the groups of internal voltage supplies may be modified from the respective external power supply voltage levels to respective operational voltage levels in a group order that is opposite to the entry group order.

    Memory Cells and Arrays of Memory Cells
    22.
    发明申请
    Memory Cells and Arrays of Memory Cells 审中-公开

    公开(公告)号：US20200286539A1

    公开(公告)日：2020-09-10

    申请号：US16878882

    申请日：2020-05-20

    Applicant: Micron Technology, Inc.

    Inventor： Yasushi Matsubara

    IPC: G11C11/22 ,  H01L27/11502 ,  G11C11/56 ,  H01L27/11514

    Abstract: A memory cell comprises first, second, third, and fourth transistors individually comprising a transistor gate. First and second ferroelectric capacitors individually have one capacitor electrode elevationally between the transistor gates of the first, second, third, and fourth transistors. Other memory cells are disclosed, as are arrays of memory cells.

    Cell bottom node reset in a memory array
    24.
    发明授权
    Cell bottom node reset in a memory array 有权

    公开(公告)号：US10311933B2

    公开(公告)日：2019-06-04

    申请号：US16054785

    申请日：2018-08-03

    Applicant: Micron Technology, Inc.

    Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

    IPC: G11C11/22 ,  G11C11/56

    Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.

    Access schemes for access line faults in a memory device
    28.
    发明授权
    Access schemes for access line faults in a memory device 有权

    公开(公告)号：US11508458B2

    公开(公告)日：2022-11-22

    申请号：US17150902

    申请日：2021-01-15

    Applicant: Micron Technology, Inc.

    Inventor： Yasushi Matsubara

    IPC: G11C29/00 ,  G06F11/10

    Abstract: Methods, systems, and devices related to access schemes for access line faults in a memory device are described. In one example, a method may include isolating a first word line of a section of a memory device from a voltage source (e.g., a deselection voltage source) during a first portion of a period when the first word line is deselected, and coupling the first word line with the voltage source during a second portion of the period when the first word line is deselected based on determining that an access operation is performed during the second portion of the period when the word line is deselected. In some examples, the method may include identifying that the first word line is associated with a fault, such as a short circuit fault with a digit line of the memory device.

    Semiconductor memory device capable of performing soft-post-package-repair operation
    29.
    发明授权
    Semiconductor memory device capable of performing soft-post-package-repair operation 有权

    公开(公告)号：US11450403B1

    公开(公告)日：2022-09-20

    申请号：US17393998

    申请日：2021-08-04

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yasushi Matsubara

    IPC: G11C29/02 ,  G11C29/00

    Abstract: Disclosed herein is an apparatus that includes a first address generator generating a first address in response to a clock signal; a second address generator generating a second address corresponding to the first address; a first detection circuit activating a first signal when the second address matches with a third address; a second detection circuit activating a second signal when the second address indicates a predetermined state; a first latch circuit latching the first address in response to the first signal; a second latch circuit latching the first address in response to the second signal; a third detection circuit activating a third signal when the first address matches with an address stored in the first latch circuit; a fourth detection circuit activating a fourth signal when the first address matches with an address stored in the second latch circuit; and a first selector selecting the third or fourth signal.

    Sequential voltage control for a memory device
    30.
    发明授权
    Sequential voltage control for a memory device 有权

    公开(公告)号：US11257549B2

    公开(公告)日：2022-02-22

    申请号：US16870670

    申请日：2020-05-08

    Applicant: Micron Technology, Inc.

    Inventor： Ki-Jun Nam ,  Takamasa Suzuki ,  Yantao Ma ,  Yasushi Matsubara

    IPC: G11C5/14 ,  G11C11/4074 ,  G11C11/417 ,  G11C16/30 ,  G11C16/12 ,  G11C7/20 ,  G11C16/04 ,  G11C16/32

    Abstract: Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.

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