公开(公告)号：US6027976A

公开(公告)日：2000-02-22

申请号：US56963

申请日：1998-04-08

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/51

CPC分类号： H01L21/28202 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66575

摘要： A semiconductor device having a gate insulating layer that includes a high permittivity layer between thin nitride layers. A first nitride layer formed on a silicon substrate to control unwanted oxidation of the substrate. A high permittivity layer is deposited on the first nitride layer, and a second nitride layer deposited on the permittivity layer. A gate electrode is formed on the second nitride layer. The second nitride layer prevents oxidation of the gate electrode from the high permittivity layer.

摘要翻译： 一种具有栅极绝缘层的半导体器件，该栅极绝缘层在薄氮化物层之间包括高介电常数层。 在硅衬底上形成的第一氮化物层，以控制衬底的不需要的氧化。 在第一氮化物层上沉积高介电常数层，沉积在介电常数层上的第二氮化物层。 在第二氮化物层上形成栅电极。 第二氮化物层防止栅电极从高电容率层的氧化。

公开(公告)号：US5937308A

公开(公告)日：1999-08-10

申请号：US824830

申请日：1997-03-26

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A substantially in situ trench isolation process is provided. The process includes forming a trench regions between active regions in a semiconductor substrate. The semiconductor substrate may be covered with a protective oxide pad and/or nitride layer. In a single chamber, an oxide is thermally grown in the trench, the nitride layer is substantially stripped, and a fill dielectric is deposited in the trench and over the active and trench regions. The invention contemplates thermal growth, etch, and deposition processes to be performed serially in a single chamber without opening the chamber. The invention further contemplates modifying or adapting a conventional process chamber to all for the in situ processing of thermal growth, etch, and deposition processes. Alternatively, a specialized chamber may be provided.

摘要翻译： 提供了基本原位的沟槽隔离工艺。 该工艺包括在半导体衬底中的有源区之间形成沟槽区域。 半导体衬底可以被保护性氧化物衬垫和/或氮化物层覆盖。 在单个室中，氧化物在沟槽中热生长，氮化物层基本剥离，并且填充电介质沉积在沟槽中以及在有源区和沟槽区上方。 本发明考虑了在单个室中串联地进行的热生长，蚀刻和沉积过程，而不打开室。 本发明进一步考虑将常规处理室修改或适应于所有用于热生长，蚀刻和沉积工艺的原位处理。 或者，可以提供专门的室。

公开(公告)号：US5872376A

公开(公告)日：1999-02-16

申请号：US812740

申请日：1997-03-06

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L27/088

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28238 ,  H01L29/513 ,  H01L29/518 ,  H01L21/28211

摘要： A semiconductor process in which a silicon film is chemically vapor deposited upon a native oxide film as part of the gate oxide formation process. The invention contemplates a method of forming a thin gate dielectric semiconductor transistor. A semiconductor substrate which includes a native oxide film on an upper region of a silicon bulk is provided and a silicon film is deposited on the native oxide film. A first oxide film is then formed on a the native oxide film by thermally oxidizing a portion of the silicon film proximal to the native oxide film such that the thin gate dielectric comprises the native oxide film and the first oxide film. Thereafter, a conductive gate is formed on the thin gate dielectric and a pair of source/drain structures are formed within a pair of source/drain regions of the semiconductor substrate. The pair of source/drain structures are laterally displaced on either side of the channel region of the semiconductor substrate. In one embodiment the process further includes the step, prior to the formation of the first oxide layer, of thinning the silicon layer by removing an upper portion of the silicon layer. In one embodiment, a barrier dielectric is deposited on an upper surface of the silicon film prior to the step of forming the first oxide film. In still another embodiment, the process further includes the step of depositing a barrier dielectric after the formation of the first oxide film and prior to the formation of the conductive gate.

公开(公告)号：US5783469A

公开(公告)日：1998-07-21

申请号：US763240

申请日：1996-12-10

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/51

CPC分类号： H01L21/28211 ,  H01L21/28176 ,  H01L21/823828 ,  H01L29/518

摘要： A method of fabricating an integrated circuit in which nitrogen is incorporated into the gate dielectric and transistor gate. The method comprises the providing of a semiconductor substrate that has a p-well and a laterally displaced n-well, each including a channel region laterally displaced between a pair of source/drain regions. Preferably, the semiconductor substrate has a resistivity of approximately 10 to 15 .OMEGA.-cm. A dielectric layer is formed on an upper surface of the semiconductor substrate. The formation of the dielectric layer preferably comprises a thermal oxidation performed at a temperature of approximately 600.degree. to 900.degree. C. and the resulting thermal oxide has a thickness less than approximately 50 angstroms. A conductive gate layer is then formed on the dielectric layer. In a preferred embodiment, the conductive gate layer is formed by chemically vapor depositing polysilicon at a pressure of less than approximately 2 torrs at a temperature in the range of approximately 500.degree. to 650.degree. C. A nitrogen bearing impurity distribution is then introduced into the conductive gate layer and the dielectric layer. The introduction of the nitrogen bearing impurity distribution is suitably accomplished by implanting a nitrogen bearing molecule such as N, N.sub.2, NO, NF.sub.3, N.sub.2 O, NH.sub.3, or other nitrogen bearing molecule. Ideally, a peak concentration of the nitrogen bearing impurity distribution is in the range of approximately 1.times.10.sup.15 to 1.times.10.sup.19 atoms/cm.sup.3 and is located proximal to an interface of the conductive gate layer and the dielectric layer. Thereafter, an anneal may be performed, preferably in a rapid thermal process, at a temperature of approximately 900.degree. to 1100.degree. C. for a duration of less than 5 minutes.

摘要翻译： 一种制造集成电路的方法，其中氮结合到栅极电介质和晶体管栅极中。 该方法包括提供具有p阱和横向移位的n阱的半导体衬底，每个阱包括在一对源/漏区之间横向移位的沟道区。 优选地，半导体衬底具有约10至15欧姆 - 厘米的电阻率。 在半导体衬底的上表面上形成介电层。 电介质层的形成优选包括在约600-900℃的温度下进行的热氧化，所得到的热氧化物的厚度小于约50埃。 然后在电介质层上形成导电栅极层。 在优选实施例中，导电栅极层是通过在约500℃至650℃的温度范围内以小于约2托的压力化学气相沉积多晶硅来形成的。然后将含氮杂质分布引入 导电栅极层和电介质层。 含氮杂质分布的引入适当地通过注入含氮分子如N，N 2，NO，NF 3，N 2 O，NH 3或其它含氮分子来完成。 理想地，含氮杂质分布的峰值浓度在约1×10 15至1×10 19原子/ cm 3的范围内，并且位于导电栅极层和电介质层的界面附近。 此后，可以在约900℃至1100℃的温度下进行退火，优选在快速热处理中进行退火持续时间少于5分钟。

公开(公告)号：US06373113B1

公开(公告)日：2002-04-16

申请号：US09073755

申请日：1998-05-06

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L2976

CPC分类号： H01L21/28211 ,  H01L21/28176 ,  H01L21/823828 ,  H01L29/518

摘要： An integrated circuit is provided in which nitrogen is incorporated into the gate dielectric and transistor gate. A method for forming the integrated circuit preferably comprises the providing of a semiconductor substrate that has a p-well and a laterally displaced n-well, each including a channel region laterally displaced between a pair of source/drain regions. Preferably, the semiconductor substrate has a resistivity of approximately 10 to 15 &OHgr;-cm. A dielectric layer is formed on an upper surface of the semiconductor substrate. The formation of the dielectric layer preferably comprises a thermal oxidation performed at a temperature of approximately 600 to 900° C. and the resulting thermal oxide has a thickness less than approximately 50 angstroms. A conductive gate layer is then formed on the dielectric layer. In a preferred embodiment, the conductive gate layer is formed by chemically vapor depositing polysilicon at a pressure of less than approximately 2 torrs at a temperature in the range of approximately 500 to 650° C. A nitrogen bearing impurity distribution is then introduced into the conductive gate layer and the dielectric layer. The introduction of the nitrogen bearing impurity distribution is suitably accomplished by implanting a nitrogen bearing molecule such as N, N2, NO, NF3, N2O, NH3, or other nitrogen bearing molecule. Ideally, a peak concentration of the nitrogen bearing impurity distribution is in the range of approximately 1×1015 to 1×1019 atoms/cm3 and is located proximal to an interface of the conductive gate layer and the dielectric layer. Thereafter, an anneal may be performed, preferably in a rapid thermal process, at a temperature of approximately 900 to 1100° C. for a duration of less than 5 minutes.

摘要翻译： 提供了一种集成电路，其中氮结合到栅极电介质和晶体管栅极中。 用于形成集成电路的方法优选地包括提供具有p阱和横向移位的n阱的半导体衬底，每个阱包括在一对源/漏区之间横向移位的沟道区。 优选地，半导体衬底具有大约10至15欧姆 - 厘米的电阻率。 在半导体衬底的上表面上形成介电层。 电介质层的形成优选包括在约600-900℃的温度下进行的热氧化，所得到的热氧化物的厚度小于约50埃。 然后在电介质层上形成导电栅极层。 在一个优选实施例中，导电栅极层通过在约500至650℃的温度范围内以小于约2托的压力下化学气相沉积多晶硅形成。然后将含氮杂质分布引入导电 栅极层和电介质层。 含氮杂质分布的引入适当地通过注入含氮分子如N，N 2，NO，NF 3，N 2 O，NH 3或其它含氮分子来完成。 理想地，含氮杂质分布的峰值浓度在约1×10 15至1×10 19原子/ cm 3的范围内，并且位于导电栅极层和电介质层的界面附近。 此后，可以在大约900至1100℃的温度下进行退火，优选在快速热处理中进行退火持续时间少于5分钟。

公开(公告)号：US06211025B1

公开(公告)日：2001-04-03

申请号：US09140009

申请日：1998-08-26

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21335

CPC分类号： H01L29/66606 ,  H01L29/456 ,  H01L29/4966

摘要： A transistor and a method of making the same are provided. The transistor includes a substrate and a gate dielectric layer positioned on the substrate that has first and second sidewall spacers. A gate electrode is positioned on the gate dielectric layer between the first and second sidewall spacers. A semiconductor layer is positioned on the substrate and adjacent the gate dielectric layer. First and second source/drain regions are provided wherein each of the first and second source/drain regions has a first portion positioned in the semiconductor layer and a second portion positioned in the substrate. Processing of the gate dielectric layer and the sidewall spacers is integrated.

摘要翻译： 提供晶体管及其制造方法。 晶体管包括衬底和位于衬底上的栅极电介质层，其具有第一和第二侧壁间隔物。 栅电极位于第一和第二侧壁间隔物之间​​的栅介质层上。 半导体层位于衬底上并与栅极介电层相邻。 提供了第一和第二源极/漏极区域，其中第一和第二源极/漏极区域中的每一个具有位于半导体层中的第一部分和位于衬底中的第二部分。 整合了栅介电层和侧壁间隔物的处理。

公开(公告)号：US06174794B1

公开(公告)日：2001-01-16

申请号：US09137275

申请日：1998-08-20

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L213205

CPC分类号： H01L29/66545 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/28518 ,  H01L21/7684 ,  H01L21/76877 ,  H01L29/51 ,  H01L29/6659

摘要： A transistor and a method of making the same are provided. The method includes the steps of forming a gate dielectric stack on the substrate that has a gate dielectric layer and forming first and second sidewall spacers adjacent the gate dielectric stack. A first portion of the gate dielectric stack is removed while a second portion thereof is left in place. First and second source/drain regions are formed in the substrate, and a conductor layer is formed over the first and second source/drain regions and on the second portion of the gate dielectric stack. The gate dielectric may be composed of a high dielectric constant material with a thin equivalent thickness of oxide. The method enables integrated processing of the gate electrode and source/drain metallization.

摘要翻译： 提供晶体管及其制造方法。 该方法包括以下步骤：在衬底上形成具有栅极电介质层并形成与栅极电介质叠层相邻的第一和第二侧壁间隔物的栅极电介质叠层。 门电介质堆叠的第一部分被移除，同时其第二部分留在原位。 在衬底中形成第一和第二源/漏区，并且在第一和第二源极/漏极区域和栅极电介质堆叠的第二部分上形成导体层。 栅极电介质可以由具有相当厚度的氧化物薄的高介电常数材料构成。 该方法实现了栅电极和源极/漏极金属化的集成处理。

公开(公告)号：US6153477A

公开(公告)日：2000-11-28

申请号：US60430

申请日：1998-04-14

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L21/28194 ,  H01L21/26506 ,  H01L21/2652 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66598 ,  H01L29/66659 ,  H01L29/7835

摘要： An integrated circuit fabrication process is provided for forming a transistor in which the channel length is mandated by the width of a gate conductor formed upon a gate dielectric having a dielectric constant greater than about 3.8. The thickness of the gate dielectric may be made sufficiently large to serve as a mask during subsequent implantation of impurities into a substrate. The gate conductor and the gate dielectric are first patterned using lithography and an etch step. In one embodiment, a masking layer is then formed across a select portion of the gate conductor and an ensuing source region of the substrate. The uncovered portion of the gate conductor is etched to expose a region of the gate dielectric. A first implant of impurities is forwarded into regions of the substrate not covered by the masking layer to form an LDD area underneath the exposed region of the gate dielectric and a heavily doped drain region laterally adjacent the LDD area. A second implant is then forwarded into the source region to form a heavily doped source region. In another embodiment, the masking layer used to originally pattern the gate conductor is etched to expose portions of the gate conductor. Those exposed portions are then removed. A single implant of impurities is forwarded into the substrate exclusive of underneath the gate conductor. LDD areas are thusly formed beneath portions of the gate dielectric not covered by the gate conductor, and source/drain regions are formed laterally adjacent the LDD areas.

摘要翻译： 提供了一种用于形成晶体管的集成电路制造工艺，其中沟道长度由形成在具有大于约3.8的介电常数的栅极电介质上的栅极导体的宽度限制。 栅极电介质的厚度可以做得足够大，以便在随后将杂质注入到衬底中用作掩模。 首先使用光刻和蚀刻步骤对栅极导体和栅极电介质进行图案化。 在一个实施例中，然后在栅极导体的选择部分和衬底的随后的源极区域上形成掩模层。 蚀刻栅极导体的未覆盖部分以暴露栅极电介质的区域。 杂质的第一种植入被转移到未被掩蔽层覆盖的衬底的区域中，以在栅极电介质的暴露区域和与LDD区域横向相邻的重掺杂漏极区域形成LDD区域。 然后将第二植入物转发到源区域中以形成重掺杂的源区。 在另一个实施例中，蚀刻用于最初构图栅极导体的掩模层以暴露栅极导体的部分。 然后去除暴露部分。 单独的杂质植入物被转移到不在栅极导体下面的衬底中。 因此，LDD区域形成在不被栅极导体覆盖的栅极电介质的部分之下，并且源极/漏极区域横向邻近LDD区域形成。

公开(公告)号：US6100204A

公开(公告)日：2000-08-08

申请号：US123657

申请日：1998-07-28

申请人： Mark I. Gardner ,  Mark C. Gilmer ,  Thomas E. Spikes, Jr.

发明人： Mark I. Gardner ,  Mark C. Gilmer ,  Thomas E. Spikes, Jr.

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L21/469

CPC分类号： H01L21/28185 ,  H01L29/517 ,  H01L29/6659 ,  H01L21/28194

摘要： A transistor and a method of making the same are provided. The method includes the step of forming a gate dielectric layer on the substrate where the gate dielectric layer is composed of an aluminum oxide containing material. A gate electrode is formed on the gate dielectric layer and first and second source/drain regions are formed in the substrate laterally separated to define a channel region beneath the gate electrode. The aluminum oxide containing material may be, for example, Al.sub.2 O.sub.3. Aluminum oxide provides for a gate dielectric with a thin equivalent thickness of oxide in a potentially single crystal form.

摘要翻译： 提供晶体管及其制造方法。 该方法包括在栅极电介质层由含氧化铝材料构成的基板上形成栅极电介质层的步骤。 栅极电极形成在栅极介电层上，并且第一和第二源极/漏极区域形成在衬底中横向分离以限定栅电极下方的沟道区域。 含氧化铝的材料可以是例如Al 2 O 3。 氧化铝以可能的单晶形式提供具有薄的当量厚度的氧化物的栅极电介质。

公开(公告)号：US6057209A

公开(公告)日：2000-05-02

申请号：US891278

申请日：1997-07-10

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/318 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76229 ,  H01L21/3185

摘要： A semiconductor device and manufacturing process in which a nitrogen bearing isolation region is formed. In one embodiment of the invention, a semiconductor device is formed by forming, in a substrate, one or more trenches each of which define an isolation region. In each trench, an insulating region is formed. In each trench over the insulating region, a nitrogen bearing region is formed. The nitrogen bearing region may, for example, be a nitride. A semiconductor device consistent with one embodiment of the invention includes a substrate having a plurality of active regions and one or more nitrogen bearing isolation regions separating the active regions. Each isolation region generally includes an insulating region adjacent the substrate and a nitrogen bearing region disposed over the insulating region and separated from the substrate by the oxide region. The nitrogen bearing region may, for example, be a nitride. The nitrogen bearing region in the isolation region generally enhances device performance and can, for example, reduce boron penetration of the isolation region.

摘要翻译： 一种其中形成有氮承载隔离区域的半导体器件和制造方法。 在本发明的一个实施例中，通过在衬底中形成一个或多个限定隔离区的沟槽形成半导体器件。 在每个沟槽中形成绝缘区域。 在绝缘区域上的每个沟槽中，形成氮气承载区域。 含氮区可以是例如氮化物。 与本发明的一个实施例一致的半导体器件包括具有多个有源区和分离有源区的一个或多个含氮隔离区的衬底。 每个隔离区域通常包括邻近衬底的绝缘区域和设置在绝缘区域上方并通过氧化物区域与衬底分离的含氮区域。 含氮区可以是例如氮化物。 隔离区域中的含氮区域通常提高器件性能，并且可以例如降低隔离区域的硼渗透。