公开(公告)号：US06204130B1

公开(公告)日：2001-03-20

申请号：US08924455

申请日：1997-08-29

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21336

CPC分类号： H01L21/28185 ,  H01L21/28123 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659

摘要： A semiconductor device having a reduced polysilicon gate electrode width and a process for manufacturing such a device is provided. Consistent with the present invention a semiconductor device is formed by forming an insulating film selective to oxide etchant over a substrate. At least one polysilicon block is formed over the insulating film. The polysilicon block is oxidized to grow an oxide layer on exposed surfaces of the polysilicon block and thereby reduce the width of the polysilicon block. The oxide layer is then removed to form a gate electrode with the remaining portion of the polysilicon block. In this manner, gate electrodes having widths smaller than the resolution of current etching techniques can be formed. In accordance with one aspect of the invention, the polysilicon gate electrode has a width less than about 0.15 microns. In accordance with another aspect, the insulating layer selective to oxide etchant is formed from a high permittivity material, such as a barium strontium titanate oxide.

摘要翻译： 提供具有降低的多晶硅栅电极宽度的半导体器件和用于制造这种器件的工艺。 根据本发明，通过在衬底上形成对氧化物蚀刻剂有选择性的绝缘膜来形成半导体器件。 在绝缘膜上形成至少一个多晶硅块。 多晶硅块被氧化以在多晶硅块的暴露表面上生长氧化物层，从而减小多晶硅块的宽度。 然后去除氧化物层以形成具有多晶硅块的剩余部分的栅电极。 以这种方式，可以形成具有小于当前蚀刻技术的分辨率的宽度的栅电极。 根据本发明的一个方面，多晶硅栅电极具有小于约0.15微米的宽度。 根据另一方面，对氧化物蚀刻剂选择性的绝缘层由诸如钛酸锶钡氧化物的高介电常数材料形成。

公开(公告)号：US06172407B2

公开(公告)日：2001-01-09

申请号：US09061552

申请日：1998-04-16

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L2972

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L21/28518 ,  H01L21/76801 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/6659

摘要： An integrated circuit fabrication process is provided in which a gate electrode including a gate dielectric and a gate conductor is formed upon a semiconductor substrate. Preferably, the gate dielectric has a dielectric constant greater than the dielectric constant of silicon dioxide. In an embodiment, sidewall spacers are formed laterally adjacent opposed sidewall surfaces of the gate electrode. An interlevel dielectric is then formed above the semiconductor substrate and selectively removed from above active regions of the semiconductor substrate to form an opening. Source and drain implant areas are formed self-aligned with the opposed sidewall spacers. A metal silicide layer may be formed across upper surfaces of the gate conductor and source and drain areas, a second interlevel dielectric deposited in the opening, and contacts formed through the second interlevel dielectric to the metal silicide. In an alternative embodiment, the gate dielectric may be formed sufficiently thick such that sidewall spacers are unnecessary to prevent silicide bridging between the gate conductor and the junction regions. In another alternative embodiment, the lightly doped drain implant areas may be formed self-aligned to the gate electrode prior to spacer formation.

摘要翻译： 提供一种集成电路制造工艺，其中在半导体衬底上形成包括栅极电介质和栅极导体的栅电极。 优选地，栅极电介质的介电常数大于二氧化硅的介电常数。 在一个实施例中，侧壁间隔件横向地形成在栅电极的相对侧壁表面上。 然后在半导体衬底之上形成层间电介质，并从半导体衬底的上述有源区选择性地移除以形成开口。 源极和漏极注入区域与相对的侧壁间隔物自对准地形成。 可以在栅极导体和源极和漏极区域的上表面，沉积在开口中的第二层间电介质和通过第二层间电介质形成的触点与金属硅化物形成金属硅化物层。 在替代实施例中，栅极电介质可以被形成为足够厚，使得不需要侧壁间隔物以防止栅极导体和接合区域之间的硅化物桥接。 在另一替代实施例中，在间隔物形成之前，轻掺杂漏极注入区域可以形成为与栅电极自对准。

公开(公告)号：US06169306A

公开(公告)日：2001-01-02

申请号：US09122833

申请日：1998-07-27

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L27108

CPC分类号： H01L29/517 ,  H01L21/28167 ,  H01L21/28194 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11543

摘要： The present invention is directed to a novel semiconductor device and a method for making same. As disclosed herein, a gate dielectric comprised of epitaxial metal oxide is positioned above a semiconducting substrate. A gate conductor comprised of an epitaxial conductive material is positioned above the gate dielectric. The method comprises forming a layer of an epitaxial metal oxide above a semiconducting substrate, forming a layer of epitaxial conductive material above the layer of epitaxial metal oxide, and forming a source/drain region.

摘要翻译： 本发明涉及一种新颖的半导体器件及其制造方法。 如本文所公开的，由外延金属氧化物组成的栅极电介质位于半导体衬底之上。 由外延导电材料构成的栅极导体位于栅极电介质的上方。 该方法包括在半导体衬底上形成外延金属氧化物层，在外延金属氧化物层之上形成外延导电材料层，形成源/漏区。

公开(公告)号：US6163060A

公开(公告)日：2000-12-19

申请号：US163673

申请日：1998-09-30

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： The present invention is directed to a new semiconductor device and a method for making same. The new semiconductor device is comprised of a gate barrier layer, a composite gate dielectric layer, a conductor layer, and at least one source/drain region formed in aemiconducting substrate. The method comprises forming the gate barrier layer, composite gate dielectric layer and conductor layer, patterning those layers, and forming at least one source/drain region in said semiconductor substrate. The composite gate dielectric layer is comprised of at least two different materials having different dielectric constants.

摘要翻译： 本发明涉及一种新的半导体器件及其制造方法。 新的半导体器件由栅极阻挡层，复合栅极电介质层，导体层和形成在半导体衬底中的至少一个源极/漏极区域组成。 该方法包括形成栅极阻挡层，复合栅极电介质层和导体层，图案化这些层，并在所述半导体衬底中形成至少一个源极/漏极区域。 复合栅极电介质层由具有不同介电常数的至少两种不同材料组成。

公开(公告)号：US6148832A

公开(公告)日：2000-11-21

申请号：US145606

申请日：1998-09-02

申请人： Mark C. Gilmer ,  Mark I. Gardner ,  Robert Paiz

发明人： Mark C. Gilmer ,  Mark I. Gardner ,  Robert Paiz

IPC分类号： B08B9/093 ,  C11D7/08 ,  C11D7/32 ,  C11D7/50 ,  C11D11/00 ,  B08B3/02 ,  B08B9/00

CPC分类号： C11D7/08 ,  B08B9/093 ,  C11D11/0041 ,  C11D7/5013 ,  C11D7/3209

摘要： An apparatus for in-situ cleaning of polysilicon-coated quartz furnaces are presented. Traditionally, disassembling and reassembling the furnace is required to clean the quartz. This procedure requires approximately four days of down time which can be very costly for a company. In addition, cleaning the quartz requires large baths filled with a cleaning agent. These baths occupy a large amount of laboratory space and require a large amount of the cleaning agent. Cleaning the furnace in-situ eliminates the very time consuming procedure of assembling and disassembling the furnace and at the same time requires less laboratory space and less amount of cleaning agent. The polysilicon remover may be either a mixture of hydrofluoric and nitric acid or TMAH. TMAH is preferred because it less hazardous than hydrofluoric acid and compatible with more materials. The cleaning agent may be introduced into the furnace either from the built-in injectors or from additionally installed injectors. If the built-in injectors are used, the input system of the furnace is cleaned in addition to the quartz inner lining.

摘要翻译： 介绍了一种用于原位清洗多晶硅涂层石英炉的设备。 传统上，需要拆卸和重新组装炉子来清洁石英。 该程序需要大约四天的停机时间，这对公司来说可能是非常昂贵的。 此外，清洁石英需要大量的填充有清洁剂的浴池。 这些浴室占据大量的实验室空间，需要大量的清洁剂。 原地清洗炉子消除了组装和拆卸炉子非常耗时的过程，同时需要更少的实验室空间和更少量的清洁剂。 多晶硅去除剂可以是氢氟酸和硝酸或TMAH的混合物。 TMAH是优选的，因为它比氢氟酸更危险，并且与更多的材料相容。 清洁剂可以从内置注射器或另外安装的注射器引入炉中。 如果使用内置注射器，除了石英内衬之外，还要清洁炉子的输入系统。

公开(公告)号：US06147004A

公开(公告)日：2000-11-14

申请号：US120056

申请日：1998-07-21

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/00

CPC分类号： H01L21/67069

摘要： The present invention is directed to a method and apparatus for reducing the thickness of a process layer. The method comprises generating a relatively high velocity gas stream comprised of active ions that will react with the process layer, and moving the wafer relative to the nozzle to effect a reduction in the thickness of the process layer. The apparatus is comprised of a process chamber, means for securing a wafer in the chamber, a nozzle having an exit that is substantially the same width as the diameter of the wafer positioned in the chamber. The apparatus further comprises a means for moving the wafer relative to the nozzle.

摘要翻译： 本发明涉及一种减小加工层厚度的方法和装置。 该方法包括产生由活性离子组成的相对高速气流，该活性离子将与处理层反应，并相对于喷嘴移动晶片以实现工艺层厚度的减小。 该装置包括处理室，用于将晶片固定在腔室中的装置，具有出口的喷嘴，该出口的宽度基本上与位于腔室中的晶片的直径相同。 该装置还包括用于相对于喷嘴移动晶片的装置。

公开(公告)号：US06114228A

公开(公告)日：2000-09-05

申请号：US120245

申请日：1998-07-21

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/3205 ,  H01L21/00

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： The present invention is directed to a new semiconductor device and a method for making same. The new semiconductor device is comprised of a gate barrier layer, a composite gate dielectric layer, a conductor layer, and at least one source/drain region formed in a semiconducting substrate. The method comprises forming the gate barrier layer, composite gate dielectric layer and conductor layer, patterning those layers, and forming at least one source/drain region in said semiconductor substrate. The composite gate dielectric layer is comprised of at least two different materials having different dielectric constants.

摘要翻译： 本发明涉及一种新的半导体器件及其制造方法。 新的半导体器件由栅极势垒层，复合栅极电介质层，导体层和形成在半导体衬底中的至少一个源极/漏极区域构成。 该方法包括形成栅极阻挡层，复合栅极电介质层和导体层，图案化这些层，并在所述半导体衬底中形成至少一个源极/漏极区。 复合栅极电介质层由具有不同介电常数的至少两种不同材料组成。

公开(公告)号：US6107146A

公开(公告)日：2000-08-22

申请号：US995113

申请日：1997-12-19

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/265 ,  H01L21/322 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/336

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/3221 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0921

摘要： A method of utilizing a non-epitaxial starting material in a CMOS semiconductor fabrication process. A bulk impurity distribution is non-selectively introduced into the starting material. The starting material includes a substantially uniformly doped wafer having a sheet resistivity in the range of approximately 5 to 25 .OMEGA.-cm. An upper boundary of the bulk impurity distribution is displaced below an upper surface of the wafer by a first depth. A peak impurity concentration of the bulk impurity distribution is greater than approximately 1.times.10.sup.19 atom/cm.sup.3. Thereafter, a barrier impurity distribution is introduced into the wafer. A peak concentration of the barrier impurity distribution is displaced below the upper surface of the wafer by a second depth. The first depth is greater than the second depth such that the barrier impurity distribution may substantially prevent the bulk impurity distribution from migrating into the upper region of the wafer. Accordingly, the wafer of the present invention comprises a lightly doped upper region over a heavily doped bulk region. The bulk layer improves latchup immunity of the CMOS integrated circuit process by providing a conductive path below the upper region.

摘要翻译： 一种在CMOS半导体制造工艺中利用非外延起始材料的方法。 大量的杂质分布被非选择性地引入到起始材料中。 起始材料包括具有约5至25欧姆 - 厘米范围内的片电阻率的基本均匀掺杂的晶片。 大块杂质分布的上边界在晶片的上表面之下移位第一深度。 本体杂质分布的峰值杂质浓度大于约1×1019原子/ cm3。 此后，将阻挡杂质分布引入晶片。 势垒杂质分布的峰值浓度在晶片的上表面下移位第二深度。 第一深度大于第二深度，使得势垒杂质分布可以基本上防止大块杂质分布迁移到晶片的上部区域。 因此，本发明的晶片包括重掺杂体区域上的轻掺杂的上部区域。 本体层通过在上部区域下方提供导电路径来提高CMOS集成电路工艺的闭锁抗扰度。

公开(公告)号：US6078089A

公开(公告)日：2000-06-20

申请号：US306953

申请日：1999-05-07

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76

CPC分类号： H01L21/28194 ,  H01L21/28097 ,  H01L21/28176 ,  H01L29/4975 ,  H01L29/517

摘要： A semiconductor device having a cobalt niobate-cobalt silicide gate electrode structure is provided. A semiconductor device, consistent with one embodiment of the invention, is formed by forming a cobalt niobate gate insulating layer over the substrate and forming a cobalt silicide layer over the cobalt niobate layer. The cobalt silicide layer and cobalt niobate gate insulating layer may, for example, be selectively removed to form at least one cobalt silicide-cobalt niobate gate electrode structure. The cobalt niobate-cobalt silicide gate electrode structure can, for example, increase the operating speed of the device as compared to conventional transistors.

摘要翻译： 提供具有铌酸钴 - 钴硅化物栅电极结构的半导体器件。 通过在衬底上形成铌酸钴栅极绝缘层并在铌酸钴层上形成钴硅化物层来形成与本发明的一个实施例一致的半导体器件。 钴硅化物层和铌酸钴栅极绝缘层可以例如被选择性地去除以形成至少一种钴铌钴铌酸盐栅电极结构。 与常规晶体管相比，铌酸钴 - 钴硅化物栅电极结构可以例如增加器件的工作速度。

公开(公告)号：US06066519A

公开(公告)日：2000-05-23

申请号：US61536

申请日：1998-04-16

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L29/51 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/28194 ,  H01L21/02164 ,  H01L21/02269 ,  H01L21/3145 ,  H01L21/31612 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor device having an oxide layer formed by outgassing oxide from a showerhead and an apparatus and process for fabricating such a device is provided. A process for fabricating a semiconductor device, in accordance with one embodiment of the invention, includes placing a substrate in a chamber having an oxide source showerhead and outgassing oxide from the showerhead to form an oxide layer on the substrate. The oxide layer may be used, at least in part, as a gate dielectric for a transistor device and may have a thickness as thin as one or two molecules. The oxide source showerhead may, for example, be formed from a block of quartz, thereby providing a silicon oxide layer on the substrate.

摘要翻译： 本发明提供一种具有通过从喷头脱气氧化物形成的氧化物层的半导体器件及其制造方法。 根据本发明的一个实施例的制造半导体器件的方法包括将衬底放置在具有氧化物源喷头和从喷头吹出氧化物的室中，以在衬底上形成氧化物层。 氧化物层可以至少部分地用作晶体管器件的栅极电介质，并且可以具有如一个或两个分子那样薄的厚度。 氧化物源喷头可以例如由石英块形成，从而在基板上提供氧化硅层。