公开(公告)号：US08053823B2

公开(公告)日：2011-11-08

申请号：US10906808

申请日：2005-03-08

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Herbert L. Ho ,  Carl J. Radens

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Herbert L. Ho ,  Carl J. Radens

IPC分类号： H01L27/108

CPC分类号： H01L21/84 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

摘要： A structure is provided herein which includes an array of trench capacitors having at least portions disposed below a buried oxide layer of an SOI substrate. Each trench capacitor shares a common unitary buried capacitor plate which includes at least a portion of a first unitary semiconductor region disposed below the buried oxide layer. An upper boundary of the buried capacitor plate defines a plane parallel to a major surface of the substrate which extends laterally throughout the array of trench capacitors. In a particular embodiment, which starts from either an SOI or a bulk substrate, trenches of the array and a contact hole are formed simultaneously, such that the contact hole extends to substantially the same depth as the trenches. The contact hole preferably has substantially greater width than the trenches such that the conductive contact via can be formed simultaneously by processing used to form trench capacitors extending along walls of the trenches.

摘要翻译： 本文提供了一种结构，其包括具有设置在SOI衬底的掩埋氧化物层下方的至少部分的沟槽电容器阵列。 每个沟槽电容器共享共同的单一掩埋电容器板，其包括设置在掩埋氧化物层下方的第一单一半导体区域的至少一部分。 掩埋电容器板的上边界限定平行于衬底的主表面的平面，横向延伸穿过整个沟槽电容器阵列。 在从SOI或体衬底开始的特定实施例中，阵列的沟槽和接触孔同时形成，使得接触孔延伸到与沟槽基本相同的深度。 接触孔优选地具有比沟槽更大的宽度，使得可以通过用于形成沿着沟槽的壁延伸的沟槽电容器的处理同时形成导电接触通孔。

公开(公告)号：US08629017B2

公开(公告)日：2014-01-14

申请号：US13417900

申请日：2012-03-12

申请人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

发明人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

IPC分类号： H01L21/8242

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10861 ,  H01L29/945

摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.

摘要翻译： 提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和 内电极 以及位于沟槽电容器上方的半导体器件。 半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。 存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

公开(公告)号：US08188528B2

公开(公告)日：2012-05-29

申请号：US12437242

申请日：2009-05-07

申请人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

发明人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

IPC分类号： H01L27/108

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10861 ,  H01L29/945

摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.

摘要翻译： 提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和 内电极 以及位于沟槽电容器上方的半导体器件。 半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。 存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

公开(公告)号：US07439149B1

公开(公告)日：2008-10-21

申请号：US11861704

申请日：2007-09-26

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Herbert L. Ho ,  Geng Wang

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Herbert L. Ho ,  Geng Wang

IPC分类号： H01L21/20

CPC分类号： H01L27/10867 ,  H01L27/0207

摘要： A method of forming a trench memory cell includes forming a trench capacitor within a substrate material, the trench capacitor including a node dielectric layer formed within a trench and a conductive capacitor electrode material formed within the trench in contact with the node dielectric layer; forming a strap mask so as cover one side of the trench and removing one or more materials from an uncovered opposite side of the trench; and forming a conductive buried strap material within the trench; wherein the strap mask is patterned in a manner such that a single-sided buried strap is defined within the trench, the single-sided buried strap configured in a manner such that the deep trench capacitor is electrically accessible at only one side of the trench.

摘要翻译： 形成沟槽存储单元的方法包括在衬底材料内形成沟槽电容器，所述沟槽电容器包括形成在沟槽内的节点电介质层和形成在所述沟槽内与所述节点电介质层接触的导电电容器电极材料; 形成带状掩模，以覆盖沟槽的一侧，并从沟槽的未覆盖的相对侧移除一种或多种材料; 以及在所述沟槽内形成导电掩埋带材料; 其中所述带掩模被图案化，使得在所述沟槽内限定单面掩埋带，所述单侧埋入带以使得所述深沟槽电容器仅在所述沟槽的一侧电可访问的方式构造。

公开(公告)号：US08946045B2

公开(公告)日：2015-02-03

申请号：US13457601

申请日：2012-04-27

申请人： John E. Barth, Jr. ,  Herbert L. Ho ,  Babar A. Khan ,  Kirk D. Peterson

发明人： John E. Barth, Jr. ,  Herbert L. Ho ,  Babar A. Khan ,  Kirk D. Peterson

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L29/02

CPC分类号： H01L28/40 ,  H01L21/84 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/66181 ,  H01L29/945

摘要： A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor.

摘要翻译： 公开了形成金属 - 绝缘体 - 金属（MIM）沟槽电容器的结构。 该结构包括具有金属层和至少一个电介质层的多层基底。 沟槽被蚀刻到衬底中，穿过金属层。 沟槽衬有与金属层接触的金属材料，金属层包括电容器的第一节点。 电介质材料将沟槽中的金属材料排列。 沟槽填充有导体。 将金属材料排列的电介质材料将导体与金属层和衬套在沟槽上的金属材料分开。 导体包括电容器的第二节点。

公开(公告)号：US08586444B2

公开(公告)日：2013-11-19

申请号：US13428004

申请日：2012-03-23

申请人： Jennifer E. Appleyard ,  John E. Barth, Jr. ,  John B. DeForge ,  Herbert L. Ho ,  Babar A. Khan ,  Kirk D. Peterson ,  Andrew A. Turner

发明人： Jennifer E. Appleyard ,  John E. Barth, Jr. ,  John B. DeForge ,  Herbert L. Ho ,  Babar A. Khan ,  Kirk D. Peterson ,  Andrew A. Turner

IPC分类号： H01L21/20

CPC分类号： H01L28/40 ,  H01L21/76898 ,  H01L27/0805 ,  H01L28/91 ,  H01L29/945

摘要： A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.

摘要翻译： 公开了半导体结构及其制造方法。 在一个实施例中，该结构包括在衬底中具有掩埋板或板的第一衬底。 每个掩埋板包括至少一个掩埋板触点和围绕至少一个掩埋板触点设置的多个深沟槽电容器。 第一氧化物层设置在第一衬底上。 可以访问第一衬底中的深沟槽电容器和掩埋板触点，以用于各种存储器和去耦应用。

公开(公告)号：US08372721B2

公开(公告)日：2013-02-12

申请号：US13343850

申请日：2012-01-05

申请人： Xiangdong Chen ,  Herbert L. Ho ,  Geng Wang

发明人： Xiangdong Chen ,  Herbert L. Ho ,  Geng Wang

IPC分类号： H01L21/336

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD1) then a conductive layer (TiN), and then a polysilicon layer (Poly). A logic PFET having substantially the same gate stack as the array NFET, and a logic NFET having a third gate stack comprising the high-K dielectric layer upon which is deposited the conductive layer (TiN) and then the polysilicon layer (Poly), without the first metal oxide layer (CD1) between the high-K dielectric layer and the conductive layer (TiN). The array NFET may therefore have a higher gate stack work function than the logic NFET, but substantially the same gate stack work function as the logic PFET.

摘要翻译： 嵌入式DRAM MOSFET包括阵列NFET，其具有包括高K电介质层的栅极堆叠，在其上沉积第一金属氧化物层（CD1），然后沉积导电层（TiN），然后沉积多晶硅层（Poly）。 具有与阵列NFET基本相同的栅极叠层的逻辑PFET，以及具有第三栅极堆叠的逻辑NFET，其包括高K电介质层，在其上沉积导电层（TiN），然后沉积多晶硅层（Poly） 高K电介质层与导电层（TiN）之间的第一金属氧化物层（CD1）。 因此，阵列NFET可以具有比逻辑NFET更高的栅极堆叠功函数，但是与逻辑PFET基本上相同的栅极堆叠功能。

公开(公告)号：US08129797B2

公开(公告)日：2012-03-06

申请号：US12141311

申请日：2008-06-18

申请人： Xiangdong Chen ,  Herbert L. Ho ,  Geng Wang

发明人： Xiangdong Chen ,  Herbert L. Ho ,  Geng Wang

IPC分类号： H01L27/088

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD1) then a conductive layer (TiN), and then a polysilicon layer (Poly). A logic PFET having substantially the same gate stack as the array NFET, and a logic NFET having a third gate stack comprising the high-K dielectric layer upon which is deposited the conductive layer (TiN) and then the polysilicon layer (Poly), without the first metal oxide layer (CD1) between the high-K dielectric layer and the conductive layer (TiN). The array NFET may therefore have a higher gate stack work function than the logic NFET, but substantially the same gate stack work function as the logic PFET.

摘要翻译： 嵌入式DRAM MOSFET包括阵列NFET，其具有包括高K电介质层的栅极堆叠，在其上沉积第一金属氧化物层（CD1），然后沉积导电层（TiN），然后沉积多晶硅层（Poly）。 具有与阵列NFET基本相同的栅极叠层的逻辑PFET，以及具有第三栅极堆叠的逻辑NFET，其包括高K电介质层，在其上沉积导电层（TiN），然后沉积多晶硅层（Poly） 高K电介质层与导电层（TiN）之间的第一金属氧化物层（CD1）。 因此，阵列NFET可以具有比逻辑NFET更高的栅极堆叠功函数，但是与逻辑PFET基本上相同的栅极堆叠功能。

公开(公告)号：US07951666B2

公开(公告)日：2011-05-31

申请号：US11872970

申请日：2007-10-16

申请人： Herbert L. Ho ,  Steven M. Shank

发明人： Herbert L. Ho ,  Steven M. Shank

IPC分类号： H01L21/8242

CPC分类号： H01L29/945 ,  H01L29/66181

摘要： Disclosed herein are embodiments of a deep trench capacitor structure and a method of forming the structure that incorporates a buried capacitor plate contact that is simultaneously formed using an adjacent deep trench. This configuration eliminates the need for additional photolithographic processing, thereby, optimizing process windows. This configuration further eliminates the need to form the deep trench capacitor through an N-doped diffusion region connector and, thereby, allows for greater design flexibility when connecting the deep trench capacitor to another integrated circuit structure (e.g., a memory cell or decoupling capacitor array). Also, disclosed herein are embodiments of another integrated circuit structure and method, and more specifically, a memory cell (e.g., a static random access memory (SRAM) cell)) and method of forming the memory cell that incorporates one or more of these deep trench capacitors in order to minimize or eliminate soft errors.

摘要翻译： 这里公开了深沟槽电容器结构的实施例以及形成结构的方法，该结构包括使用相邻的深沟槽同时形成的埋入电容器板接触。 该配置消除了对附加光刻处理的需要，从而优化处理窗口。 该配置还消除了通过N掺杂扩散区连接器形成深沟槽电容器的需要，从而当将深沟槽电容器连接到另一集成电路结构（例如，存储器单元或去耦电容器阵列 ）。 此外，本文公开的是另一集成电路结构和方法，更具体地，存储器单元（例如，静态随机存取存储器（SRAM）单元））的实施例）以及形成包含这些深度中的一个或多个的存储器单元的方法 沟槽电容器，以减少或消除软错误。

公开(公告)号：US20100038725A1

公开(公告)日：2010-02-18

申请号：US12190220

申请日：2008-08-12

申请人： Michael P. Chudzik ,  Martin M. Frank ,  Herbert L. Ho ,  Mark J. Hurley ,  Rashmi Jha ,  Naim Moumen ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri

发明人： Michael P. Chudzik ,  Martin M. Frank ,  Herbert L. Ho ,  Mark J. Hurley ,  Rashmi Jha ,  Naim Moumen ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/49 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4958 ,  H01L29/517

摘要： Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.

摘要翻译： 提出了离子注入来改变双功能金属栅极整合的有效功函数。 一种方法可以包括在第一类型场效应晶体管（FET）区域和第二类型FET区域上形成高介电常数（高k）层; 在第一型FET区域和第二类型FET区域上形成具有与第一型FET兼容的第一有效功函数的金属层; 以及通过在第二类型FET区域上将金属注入到金属层中，将第一有效功函数改变为第二类不同的有效功函数。