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    Deep trench capacitor and method
    1.
    发明授权
    Deep trench capacitor and method 有权
    深沟槽电容器及方法

    公开(公告)号：US07951666B2

    公开(公告)日：2011-05-31

    申请号：US11872970

    申请日：2007-10-16

    申请人： Herbert L. Ho ,  Steven M. Shank

    发明人： Herbert L. Ho ,  Steven M. Shank

    IPC分类号： H01L21/8242

    CPC分类号： H01L29/945 ,  H01L29/66181

    摘要： Disclosed herein are embodiments of a deep trench capacitor structure and a method of forming the structure that incorporates a buried capacitor plate contact that is simultaneously formed using an adjacent deep trench. This configuration eliminates the need for additional photolithographic processing, thereby, optimizing process windows. This configuration further eliminates the need to form the deep trench capacitor through an N-doped diffusion region connector and, thereby, allows for greater design flexibility when connecting the deep trench capacitor to another integrated circuit structure (e.g., a memory cell or decoupling capacitor array). Also, disclosed herein are embodiments of another integrated circuit structure and method, and more specifically, a memory cell (e.g., a static random access memory (SRAM) cell)) and method of forming the memory cell that incorporates one or more of these deep trench capacitors in order to minimize or eliminate soft errors.

    摘要翻译： 这里公开了深沟槽电容器结构的实施例以及形成结构的方法，该结构包括使用相邻的深沟槽同时形成的埋入电容器板接触。 该配置消除了对附加光刻处理的需要，从而优化处理窗口。 该配置还消除了通过N掺杂扩散区连接器形成深沟槽电容器的需要，从而当将深沟槽电容器连接到另一集成电路结构（例如，存储器单元或去耦电容器阵列 ）。 此外，本文公开的是另一集成电路结构和方法，更具体地，存储器单元（例如，静态随机存取存储器（SRAM）单元））的实施例）以及形成包含这些深度中的一个或多个的存储器单元的方法 沟槽电容器，以减少或消除软错误。

    Deep trench capacitor and method of making same
    3.
    发明授权
    Deep trench capacitor and method of making same 失效
    深沟槽电容器及其制作方法

    公开(公告)号：US07694262B2

    公开(公告)日：2010-04-06

    申请号：US11872787

    申请日：2007-10-16

    申请人： Timothy Wayne Kemerer ,  Robert Mark Rassel ,  Steven M. Shank ,  Francis Roger White

    发明人： Timothy Wayne Kemerer ,  Robert Mark Rassel ,  Steven M. Shank ,  Francis Roger White

    IPC分类号： G06F17/50

    CPC分类号： H01L29/945 ,  H01L29/66181

    摘要： A trench capacitor, method of forming a trench capacitor and a design structure for a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers.

    摘要翻译： 沟槽电容器，形成沟槽电容器的方法以及沟槽电容器的设计结构。 所述沟槽电容器包括：单晶硅衬底中的沟槽，在所述沟槽的侧壁和底部上的保形电介质衬垫; 填充未被衬垫填充的沟槽区域的导电多晶硅内板; 衬底中的导电掺杂外板，其围绕所述沟槽的侧壁和底部; 衬底中的掺杂硅区域; 在所述衬底的顶表面上暴露的所述掺杂硅区域的表面区域上的第一导电金属硅化物层; 在所述内板的在所述基板的顶表面处暴露的表面区域上的第二导电金属硅化物层; 以及在所述第一和第二金属硅化物层之间的所述衬底的顶表面上的绝缘环。

    DEEP TRENCH CAPACITOR AND METHOD OF MAKING SAME
    4.
    发明申请
    DEEP TRENCH CAPACITOR AND METHOD OF MAKING SAME 有权
    深度电容电容器及其制造方法

    公开(公告)号：US20080315274A1

    公开(公告)日：2008-12-25

    申请号：US11767616

    申请日：2007-06-25

    申请人： Timothy Wayne Kemerer ,  Robert Mark Rassel ,  Steven M. Shank ,  Francis Roger White

    发明人： Timothy Wayne Kemerer ,  Robert Mark Rassel ,  Steven M. Shank ,  Francis Roger White

    IPC分类号： H01L29/92 ,  H01L21/20

    CPC分类号： H01L29/945 ,  H01L28/40

    摘要： A trench capacitor and method of forming a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers.

    摘要翻译： 沟槽电容器和形成沟槽电容器的方法。 所述沟槽电容器包括：单晶硅衬底中的沟槽，在所述沟槽的侧壁和底部上的保形电介质衬垫; 填充未被衬垫填充的沟槽区域的导电多晶硅内板; 衬底中的导电掺杂外板，其围绕所述沟槽的侧壁和底部; 衬底中的掺杂硅区域; 在所述衬底的顶表面上暴露的所述掺杂硅区域的表面区域上的第一导电金属硅化物层; 在所述内板的在所述基板的顶表面处暴露的表面区域上的第二导电金属硅化物层; 以及在所述第一和第二金属硅化物层之间的所述衬底的顶表面上的绝缘环。

    Apparatus and method for forming an oxynitride insulating layer on a semiconductor wafer
    6.
    发明授权
    Apparatus and method for forming an oxynitride insulating layer on a semiconductor wafer 失效
    在半导体晶片上形成氧氮化物绝缘层的装置和方法

    公开(公告)号：US06346487B1

    公开(公告)日：2002-02-12

    申请号：US09803503

    申请日：2001-03-10

    申请人： Douglas A. Buchanan ,  Evgeni P. Gousev ,  Carol J. Heenan ,  Wade J. Hodge ,  Steven M. Shank ,  Patrick R. Varekamp

    发明人： Douglas A. Buchanan ,  Evgeni P. Gousev ,  Carol J. Heenan ,  Wade J. Hodge ,  Steven M. Shank ,  Patrick R. Varekamp

    IPC分类号： H01L2131

    CPC分类号： H01L21/28185 ,  C23C16/308 ,  C23C16/401 ,  C23C16/452 ,  C23C16/453 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/2822 ,  H01L21/3115 ,  H01L21/3144 ,  H01L29/518

    摘要： An apparatus and method of forming an oxynitride insulating layer on a substrate performed by putting the substrate at a first temperature within the main chamber of a furnace, exposing the substrate to a nitrogen containing gas at a second temperature which is higher than the first temperature, and growing the oxynitride layer on the substrate within the main chamber in the presence of post-combusted gases. The higher temperature nitrogen containing gases are combusted in a chamber outside the main chamber. The higher temperature is in the range of 800 to 1200° C., and preferably 950° C. In a second embodiment, distributed N2O gas injectors within the main chamber deliver the nitrogen containing gas. The nitrogen containing gas is pre-heated outside the chamber. The nitrogen containing gas is then delivered to a gas manifold that splits the gas flow and directs the gas to a number of gas injectors, preferably two to four injectors within the main process tube. Gas injection orifices on the order of several millimeters then distribute the pre-decomposed gas to the wafers, producing a more uniformly N-doped wafer load in a batch furnace.

    摘要翻译： 一种在基板上形成氧氮化物绝缘层的装置和方法，其通过将基板置于炉的主室内的第一温度下，在高于第一温度的第二温度下将基板暴露于含氮气体， 并在存在后燃烧气体的情况下在主室内的衬底上生长氧氮化物层。 较高温度的含氮气体在主室外的室内燃烧。 较高的温度在800至1200℃的范围内，优选950℃。在第二实施例中，主室内的分布式N2O气体喷射器输送含氮气体。 含氮气体在室外预加热。 然后将含氮气体输送到气体歧管，气体歧管分裂气体流并将气体引导到主处理管内的多个气体喷射器，优选两至四个喷射器。 大约数毫米的气体注入孔然后将预分解的气体分配到晶片，在间歇炉中产生更均匀的N掺杂晶片负载。

    MEMS PROCESS METHOD FOR HIGH ASPECT RATIO STRUCTURES
    7.
    发明申请
    MEMS PROCESS METHOD FOR HIGH ASPECT RATIO STRUCTURES 失效
    用于高比例比例结构的MEMS工艺方法

    公开(公告)号：US20120149133A1

    公开(公告)日：2012-06-14

    申请号：US12966397

    申请日：2010-12-13

    申请人： Charles J. Parrish ,  Steven M. Shank

    发明人： Charles J. Parrish ,  Steven M. Shank

    IPC分类号： H01L21/66

    CPC分类号： H01L22/20 ,  B81C1/00619 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3083 ,  H01L22/12

    摘要： Methods for the controlled manufacture of high aspect ratio features. The method may include forming a layer stack on a top surface of a substrate and forming features in the layers of the layer stack. The high aspect ratio features may be defined using a resist layer that is patterned with a photolithographic condition. After removing at least one of the layers removed from the top of the layer stack, a feature dimension may be measured for features at different locations on the substrate. The method may further include changing the photolithographic condition based on the measured dimension and processing another substrate using the changed photolithographic condition.

    摘要翻译： 用于控制制造高纵横比特征的方法。 该方法可以包括在衬底的顶表面上形成层堆叠并且在层堆叠的层中形成特征。 可以使用用光刻条件图案化的抗蚀剂层来限定高纵横比特征。 在去除从层堆叠的顶部去除的至少一层之后，可以测量基板上不同位置处的特征的特征尺寸。 该方法还可以包括基于所测量的尺寸来改变光刻条件，并且使用改变的光刻条件来处理另一衬底。

    Method of manufacturing a dual contact trench capacitor
    8.
    发明授权
    Method of manufacturing a dual contact trench capacitor 有权
    制造双接触沟槽电容器的方法

    公开(公告)号：US07897473B2

    公开(公告)日：2011-03-01

    申请号：US12181335

    申请日：2008-07-29

    申请人： Timothy W. Kemerer ,  Jenifer E. Lary ,  James S. Nakos ,  Steven M. Shank

    发明人： Timothy W. Kemerer ,  Jenifer E. Lary ,  James S. Nakos ,  Steven M. Shank

    IPC分类号： H01L21/20

    CPC分类号： H01L27/0733 ,  H01L21/76229 ,  H01L28/90

    摘要： A method of manufacturing a dual contact trench capacitor is provided. The method includes forming a first plate provided within a trench and isolated from a wafer body by a first insulator layer formed in the trench. The method further includes forming a second plate provided within the trench and isolated from the wafer body and the first plate by a second insulator layer formed in the trench.

    摘要翻译： 提供一种制造双接触沟槽电容器的方法。 该方法包括形成设置在沟槽内的第一板，并且通过形成在沟槽中的第一绝缘体层与晶片本体隔离。 该方法还包括形成设置在沟槽内的第二板，并且通过在沟槽中形成的第二绝缘体与晶片本体和第一板隔离。

    Deep trench capacitor and method of making same
    9.
    发明授权
    Deep trench capacitor and method of making same 有权
    深沟槽电容器及其制作方法

    公开(公告)号：US07812388B2

    公开(公告)日：2010-10-12

    申请号：US11767616

    申请日：2007-06-25

    申请人： Timothy Wayne Kemerer ,  Robert Mark Rassel ,  Steven M Shank ,  Francis Roger White

    发明人： Timothy Wayne Kemerer ,  Robert Mark Rassel ,  Steven M Shank ,  Francis Roger White

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L29/945 ,  H01L28/40

    摘要： A trench capacitor and method of forming a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers.

    摘要翻译： 沟槽电容器和形成沟槽电容器的方法。 所述沟槽电容器包括：单晶硅衬底中的沟槽，在所述沟槽的侧壁和底部上的保形电介质衬垫; 填充未被衬垫填充的沟槽区域的导电多晶硅内板; 衬底中的导电掺杂外板，其围绕所述沟槽的侧壁和底部; 衬底中的掺杂硅区域; 在所述衬底的顶表面上暴露的所述掺杂硅区域的表面区域上的第一导电金属硅化物层; 在所述内板的在所述基板的顶表面处暴露的表面区域上的第二导电金属硅化物层; 以及在所述第一和第二金属硅化物层之间的所述衬底的顶表面上的绝缘环。