公开(公告)号：US07571417B2

公开(公告)日：2009-08-04

申请号：US11012494

申请日：2004-12-16

申请人： Kyoko Izuha ,  Shigeki Nojima ,  Toshiya Kotani ,  Satoshi Tanaka

发明人： Kyoko Izuha ,  Shigeki Nojima ,  Toshiya Kotani ,  Satoshi Tanaka

IPC分类号： G06F17/50

CPC分类号： G03F7/70441 ,  G03F1/36

摘要： A pattern verification method includes preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, and computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges. The positional displacement is a displacement between first point and the evaluation point. The method further includes computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics.

摘要翻译： 模式验证方法包括在衬底上制备期望图案和形成期望图案的掩模图案，在期望图案的边缘上限定至少一个评估点，限定至少一个过程参数以计算所转移/形成的图案，定义 针对每个处理参数的参考值和可变范围，并且计算与评估点相对应的每个第一点的位置偏移，使用校正掩模图案计算的第一点和通过改变处理参数获得的参数值的多个组合 在可变范围内或在相应的可变范围内。 位置偏移是第一点与评价点之间的位移。 该方法还包括计算每个评估点的位置偏移的统计量，并根据统计信息输出修改掩模图案的信息。

公开(公告)号：US20090077530A1

公开(公告)日：2009-03-19

申请号：US12269705

申请日：2008-11-12

申请人： TOSHIYA KOTANI ,  Shigeki Nojima ,  Shimon Maeda

发明人： TOSHIYA KOTANI ,  Shigeki Nojima ,  Shimon Maeda

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

公开(公告)号：US20090077529A1

公开(公告)日：2009-03-19

申请号：US12269687

申请日：2008-11-12

申请人： TOSHIYA KOTANI ,  Shigeki Nojima ,  Shimon Maeda

发明人： TOSHIYA KOTANI ,  Shigeki Nojima ,  Shimon Maeda

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

摘要翻译： 公开了一种相对于设计图案的微小步骤校正设计图案的设计图案校正方法，其包括提取从设计图案的顶点延伸的两个边缘中的至少一个，测量提取的边缘的长度， 确定测量的边缘的长度是否短于预定值，如果确定提取的边缘的长度短于预定值，则提取连接到所提取的边缘的两个顶点，并且重新设计匹配的设计模式 两个提取的顶点的位置彼此相对。

公开(公告)号：US07213226B2

公开(公告)日：2007-05-01

申请号：US10920397

申请日：2004-08-18

申请人： Toshiya Kotani ,  Shigeki Nojima

发明人： Toshiya Kotani ,  Shigeki Nojima

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A method of correcting a finish pattern dimension by using OPC when a design pattern is formed on a wafer, including selecting and determining a first design pattern included in the design pattern; acquiring a measurement value of a first finish pattern dimension when the first design pattern is formed on a wafer; determining a first calculation model by using the first finish pattern dimension; selecting and determining a second design pattern from the design pattern except for the first design pattern; performing first simulation by using the first calculation model, and calculating a second finish pattern dimension when the second design pattern is formed on a wafer; determining a second calculation model for performing second simulation which is faster than the first simulation, by using the first and second finish pattern dimensions; and performing the second simulation by using the second calculation model, and calculating a third finish pattern dimension of a third design pattern of the design pattern except for the first and second design patterns.

摘要翻译： 一种当在晶片上形成设计图案时通过使用OPC来校正精加工图案尺寸的方法，包括选择和确定包括在设计图案中的第一设计图案; 当在晶片上形成第一设计图案时，获取第一精加工图案尺寸的测量值; 通过使用所述第一完成图案维度来确定第一计算模型; 从除了第一设计图案之外的设计图案中选择和确定第二设计图案; 通过使用第一计算模型执行第一模拟，以及当在晶片上形成第二设计图案时计算第二精加工图案尺寸; 通过使用第一和第二完成图案尺寸，确定用于执行比第一模拟更快的第二模拟的第二计算模型; 以及通过使用所述第二计算模型执行所述第二模拟，以及计算除了所述第一和第二设计图案之外的所述设计图案的第三设计图案的第三精加工图案尺寸。

公开(公告)号：US20060039596A1

公开(公告)日：2006-02-23

申请号：US11205017

申请日：2005-08-17

申请人： Shigeki Nojima ,  Hiroshi Motoki ,  Takahiro Ikeda ,  Satoshi Tanaka ,  Takeshi Ito

发明人： Shigeki Nojima ,  Hiroshi Motoki ,  Takahiro Ikeda ,  Satoshi Tanaka ,  Takeshi Ito

IPC分类号： G06K9/00

CPC分类号： G03F1/84

摘要： A pattern measuring method includes preparing a substrate comprising a pattern, extracting a place to be measured on the substrate based on a simulation using pattern data relating to the pattern as input data, generating measurement information for measuring a physical quantity of the place to be measured by a measuring apparatus, and measuring the place to be measured based on the measurement information by the measuring apparatus.

摘要翻译： 图案测量方法包括：准备包括图案的基板，基于使用与图案相关的图案数据作为输入数据的模拟，在基板上提取待测量的地方，生成用于测量待测位置的物理量的测量信息 通过测量装置，并且基于测量装置的测量信息来测量待测量的位置。

公开(公告)号：US20060033049A1

公开(公告)日：2006-02-16

申请号：US11200176

申请日：2005-08-10

申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Shigeki Nojima ,  Soichi Inoue

发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Shigeki Nojima ,  Soichi Inoue

IPC分类号： G21K5/10

CPC分类号： H01J37/3026 ,  G03F1/36 ,  G03F1/68

摘要： A design pattern data preparing method including preparing first mask pattern data based on first design pattern data, predicting a wafer pattern to be formed on a wafer corresponding to the first mask pattern based on the first mask pattern data, judging whether or not a finite difference between the predicted wafer pattern and the pattern to be formed on the wafer is within a predetermined allowable variation amount, correcting a portion of the first design pattern data selectively, the portion including a part corresponding to the finite difference when the finite difference is not within the allowable variation amount, and preparing second design pattern data by synthesizing the first mask pattern data corresponding to the portion including the part selectively corrected and data obtained by eliminating the first mask pattern data corresponding to the portion including the part selectively corrected from the first mask pattern data.

公开(公告)号：US06333203B1

公开(公告)日：2001-12-25

申请号：US09383960

申请日：1999-08-27

申请人： Shigeki Nojima ,  Koji Hashimoto

发明人： Shigeki Nojima ,  Koji Hashimoto

IPC分类号： H01L2166

CPC分类号： H01L22/26

摘要： In a method of forming a resist pattern, a simulation is in advance carried out to select a thickness of the resist film and a thickness of the underlying film to have certain values so that the contrast of the latent image becomes a threshold value or less. The simulation includes the steps of calculating a light intensity profile of a latent image formed in a resist film in a depth direction thereof by an exposure, slicing the light intensity profile of the latent image in the depth direction of the resist film, at a desired position, obtaining a maximum value and a minimum value of light intensity of a latent image at the position where the latent image profile is sliced, calculating a contrast of the latent image on the basis of the maximum and minimum values of the light intensity of the latent image, and determining a thickness of the resist film and a thickness of an underlying film of the resist film to have values so that the contrast becomes a threshold value or less. A resist pattern is then formed on a semiconductor substrate on the basis of the values of the thicknesses determined in the determining step.

摘要翻译： 在形成抗蚀剂图案的方法中，预先进行模拟以选择抗蚀剂膜的厚度和底层膜的厚度以具有某些值，使得潜像的对比度变为阈值以下。 模拟包括以下步骤：通过曝光来计算在其深度方向上形成在抗蚀剂膜中的潜像的光强度分布，将潜像的深度方向上的潜像的光强度分布切割成期望的步骤 位置，获得在潜像图像被切片的位置处的潜像的光强度的最大值和最小值，基于所述潜像的光强度的最大值和最小值来计算潜像的对比度 潜像，并且确定抗蚀剂膜的厚度和抗蚀剂膜的基底膜的厚度具有使得对比度变为阈值或更小的值的值。 基于在确定步骤中确定的厚度的值，在半导体衬底上形成抗蚀剂图案。

公开(公告)号：US08402407B2

公开(公告)日：2013-03-19

申请号：US13010130

申请日：2011-01-20

申请人： Shigeki Nojima

发明人： Shigeki Nojima

IPC分类号： G06F17/50

CPC分类号： G06T7/001 ,  G03F1/36 ,  G06F17/5081 ,  G06T2207/30148

摘要： A semiconductor integrated circuit pattern verification method includes executing simulation to obtain a simulation pattern to be formed on a substrate on the basis of a semiconductor integrated circuit design pattern, comparing the simulation pattern and the design pattern that is required on the substrate to detect a first difference value, extracting error candidates at which the first difference value is not less than a first predetermined value, comparing pattern shapes at the error candidates to detect a second difference value, combining, into one group, patterns whose second difference values are not more than a second predetermined value, and extracting a predetermined number of patterns from each group and verifying error candidates of the extracted patterns.

摘要翻译： 半导体集成电路图案验证方法包括执行模拟，以基于半导体集成电路设计图案获得要在基板上形成的模拟图案，比较基板上所需的模拟图案和设计图案，以检测第一 差分值，提取第一差值不小于第一预定值的错误候选，比较错误候选的图案形状以检测第二差值，将第二差值不大于 第二预定值，并且从每个组提取预定数量的模式并验证提取的模式的错误候选。

公开(公告)号：US20120198396A1

公开(公告)日：2012-08-02

申请号：US13237854

申请日：2011-09-20

申请人： Masanari KAJIWARA ,  Sachiko Kobayashi ,  Satoshi Tanaka ,  Kazuhiro Takahata ,  Shigeki Nojima ,  Toshiya Kotani ,  Shimon Maeda

发明人： Masanari KAJIWARA ,  Sachiko Kobayashi ,  Satoshi Tanaka ,  Kazuhiro Takahata ,  Shigeki Nojima ,  Toshiya Kotani ,  Shimon Maeda

IPC分类号： G06F17/50

CPC分类号： H01L22/20 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of optimizing a semiconductor device manufacturing process according to an embodiment is a method of optimizing a semiconductor device manufacturing process in which a pattern based on circuit design is formed. The method of optimizing a semiconductor device manufacturing process according to the embodiment includes: at the time of calculation of a statistic amount based on a distribution of differences at a plurality of sites between a pattern formed by a first exposing apparatus in a first condition and a pattern formed by a second exposing apparatus in a second condition, calculating the statistic amount after applying weighting to the differences based on information on an electrical characteristic; and repeating the calculating with the second condition being changed, and selecting an condition in which the total sum becomes a minimum or equal to or less than a standard value as an optimized condition of the second exposing apparatus.

摘要翻译： 根据实施例的优化半导体器件制造工艺的方法是优化其中形成基于电路设计的图案的半导体器件制造工艺的方法。 根据实施例的半导体器件制造方法的优化方法包括：在基于在第一状态下由第一曝光装置形成的图案与第一状态之间的多个位置处的差异的分布的统计量的计算时， 在第二状态下由第二曝光装置形成的图案，基于关于电特性的信息对所述差进行加权计算后的统计量; 并重复进行第二条件的计算，并且选择总和变为最小或等于或小于标准值的条件作为第二曝光装置的优化条件。

公开(公告)号：US08078996B2

公开(公告)日：2011-12-13

申请号：US12457751

申请日：2009-06-19

申请人： Kyoko Izuha ,  Shigeki Nojima ,  Toshiya Kotani ,  Satoshi Tanaka

发明人： Kyoko Izuha ,  Shigeki Nojima ,  Toshiya Kotani ,  Satoshi Tanaka

IPC分类号： G06F17/50

CPC分类号： G03F7/70441 ,  G03F1/36

摘要： A pattern verification method includes preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, and computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges. The positional displacement is a displacement between first point and the evaluation point. The method further includes computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics.

摘要翻译： 模式验证方法包括在衬底上制备期望图案和形成期望图案的掩模图案，在期望图案的边缘上限定至少一个评估点，限定至少一个过程参数以计算所转移/形成的图案，定义 针对每个处理参数的参考值和可变范围，并且计算与评估点相对应的每个第一点的位置偏移，使用校正掩模图案计算的第一点和通过改变处理参数获得的参数值的多个组合 在可变范围内或在相应的可变范围内。 位置偏移是第一点与评价点之间的位移。 该方法还包括计算每个评估点的位置偏移的统计量，并根据统计信息输出修改掩模图案的信息。