公开(公告)号：US5872482A

公开(公告)日：1999-02-16

申请号：US673997

申请日：1996-07-01

Applicant: Mathias Krauss

Inventor： Mathias Krauss

IPC: H03F3/45 ,  G06G7/12

CPC classification number: H03F3/45475

Abstract: An amplifier circuit for analog-signal processing has an operational amplifier having an output, an inverting input, and supply inputs for accepting a single supply potential and a reference potential. The operational amplifier has a noninverting input capable of accepting a signal voltage of a varying analog signal input thereto which has a positive value range and a negative value range relative to the reference potential. The output is fed back to the inverting input and the operational amplifier has a differential amplifier having first and second field-effect transistors. The first field-effect transistor has a gate connected to the noninverting input of the operational amplifier and the second field-effect transistor has a gate connected to the inverting input. The first field-effect transistor has a threshold voltage lower than a threshold voltage of the second field-effect transistor by an amount at least equal to an amount of a value range of the analog signal voltage outside a range defined by the single supply potential and the reference potential to offset an output signal at the output to within the range defined by the single supply potential and the reference potential.

Abstract translation: 用于模拟信号处理的放大器电路具有运算放大器，其具有用于接受单个电源电位和参考电位的输出，反相输入和电源输入。 运算放大器具有能够接受输入到其的变化的模拟信号的信号电压的同相输入，该信号电压具有相对于参考电位的正值范围和负值范围。 输出反馈到反相输入，运算放大器具有一个具有第一和第二场效应晶体管的差分放大器。 第一场效应晶体管具有连接到运算放大器的非反相输入的栅极，第二场效应晶体管具有连接到反相输入端的栅极。 第一场效应晶体管的阈值电压低于第二场效应晶体管的阈值电压，其量至少等于由单电源电位限定的范围之外的模拟信号电压的值范围的量;以及 将输出端的输出信号偏移到由单电源电压和参考电位限定的范围内的参考电位。

公开(公告)号：US08410969B2

公开(公告)日：2013-04-02

申请号：US13144046

申请日：2010-01-12

Applicant: Mathias Krauss ,  Maha Jaafar ,  Ke Wang ,  Eric Hoffman

Inventor： Mathias Krauss ,  Maha Jaafar ,  Ke Wang ,  Eric Hoffman

IPC: H03M1/12

CPC classification number: H03M1/60

Abstract: A capacitive-to-digital converter is provided which includes: sensor, offset and reference capacitors, an integrator circuit and a demodulation circuit. The sensor capacitor is switched according to a first clock and the offset capacitor according to a second clock, which has a higher switching frequency. The reference capacitor is switched according to a return signal from the converter's output. The integrator circuit includes an integrator capacitor, and has first and second nodes, with the sensor, offset and reference capacitors each being switched to the first and second nodes based on the respective first clock, second clock or return signal. The demodulation circuit receives and converts output of the integrator circuit into a digital output. The higher frequency clocking of the offset capacitor allows for a reduction in capacitance of the offset, reference or integrator capacitor, and the multiclocking of the converter allows for use of a multireferencing to the sensor capacitor.

Abstract translation: 提供了一种电容数字转换器，其包括：传感器，偏移和参考电容器，积分器电路和解调电路。 根据第一时钟传感器电容器和根据具有较高开关频率的第二时钟的偏移电容器来切换传感器电容器。 参考电容根据转换器输出的返回信号进行切换。 积分器电路包括积分电容器，并且具有第一和第二节点，传感器，偏移和参考电容器各自基于相应的第一时钟，第二时钟或返回信号切换到第一和第二节点。 解调电路将积分电路的输出接收并转换为数字输出。 偏移电容器的较高频率时钟允许偏移，参考或积分电容器的电容减小，并且转换器的多锁定器允许使用多传感器传感器电容器。

公开(公告)号：US20120112947A1

公开(公告)日：2012-05-10

申请号：US13144046

申请日：2010-01-12

Applicant: Mathias Krauss ,  Maha Jaafar ,  Ke Wang ,  Eric Hoffman

Inventor： Mathias Krauss ,  Maha Jaafar ,  Ke Wang ,  Eric Hoffman

IPC: H03M1/12

CPC classification number: H03M1/60

Abstract: A capacitive-to-digital converter is provided which includes: sensor, offset and reference capacitors, an integrator circuit and a demodulation circuit. The sensor capacitor is switched according to a first clock and the offset capacitor according to a second clock, which has a higher switching frequency. The reference capacitor is switched according to a return signal from the converter's output. The integrator circuit includes an integrator capacitor, and has first and second nodes, with the sensor, offset and reference capacitors each being switched to the first and second nodes based on the respective first clock, second clock or return signal. The demodulation circuit receives and converts output of the integrator circuit into a digital output. The higher frequency clocking of the offset capacitor allows for a reduction in capacitance of the offset, reference or integrator capacitor, and the multiclocking of the converter allows for use of a multireferencing to the sensor capacitor.

Abstract translation: 提供了一种电容数字转换器，其包括：传感器，偏移和参考电容器，积分器电路和解调电路。 根据第一时钟传感器电容器和根据具有较高开关频率的第二时钟的偏移电容器来切换传感器电容器。 参考电容根据转换器输出的返回信号进行切换。 积分器电路包括积分电容器，并且具有第一和第二节点，传感器，偏移和参考电容器各自基于相应的第一时钟，第二时钟或返回信号切换到第一和第二节点。 解调电路将积分电路的输出接收并转换为数字输出。 偏移电容器的较高频率时钟允许偏移，参考或积分电容器的电容减小，并且转换器的多锁定器允许使用多传感器传感器电容器。

公开(公告)号：US20120098557A1

公开(公告)日：2012-04-26

申请号：US13144036

申请日：2010-01-12

Applicant: Mathias Krauss ,  Sam Koblenski

Inventor： Mathias Krauss ,  Sam Koblenski

IPC: G01R31/3187

CPC classification number: H03M1/109 ,  H03M1/12

Abstract: Method and system are provided for evaluating linearity of a capacitive-to-digital converter (CDC) of a capacitive sensor integrated circuit chip. The evaluating employs multiple test capacitors, which may be on-chip with the CDC, and includes: obtaining capacitance values for the multiple test capacitors and parasitic capacitances of a first input A and a second input B to the capacitive-to-digital converter; applying the multiple test capacitors in multiple permutations to the first input A and the second input B, and for each of at least some permutations, determining an error between an expected output of the CDC using the obtained capacitance values and an actual measured output of the CDC; and determining linearity error for the CDC using the determined errors for the permutations of applying the multiple test capacitors to the first input A and the second input B of the CDC.

Abstract translation: 提供了用于评估电容式传感器集成电路芯片的电容 - 数字转换器（CDC）的线性度的方法和系统。 该评估采用多个测试电容器，其可以与CDC在芯片上，并且包括：获得多个测试电容器的电容值和第一输入端A和第二输入端B到电容 - 数字转换器的寄生电容; 将多个测试电容器以多个排列施加到第一输入端A和第二输入端B，并且对于至少一些排列中的每一个，使用所获得的电容值确定CDC的期望输出之间的误差和 CDC; 以及使用所确定的用于将多个测试电容器施加到CDC的第一输入A和第二输入B的排列的误差来确定CDC的线性误差。

公开(公告)号：US20120013391A1

公开(公告)日：2012-01-19

申请号：US13143618

申请日：2010-01-07

Applicant: Mathias Krauss

Inventor： Mathias Krauss

IPC: H03K17/041

CPC classification number: H03K17/063 ,  H03K17/04106

Abstract: An adaptive switch circuit is provided, which includes a CMOS switch, an off-level voltage generator, and a booster circuit. The CMOS switch includes first PMOS and NMOS coupled transistors. The generator provides, via first and second outputs, first and second voltage levels, and includes second PMOS and NMOS transistors. The second PMOS transistor is series connected between VDD and a first bias source and the second NMOS transistor is series connected between VSS and a second bias source. The booster circuit, which is coupled to the generator between its outputs, and to the PMOS and NMOS gates of the CMOS switch, capacitively stores during off level first and second boost voltages, which are coupled to the PMOS and NMOS gates. The boost voltages are offset from VDD and VSS, respectively, each by approximately a threshold voltage of the respective transistor type.

Abstract translation: 提供一种自适应开关电路，其包括CMOS开关，截止电压发生器和升压电路。 CMOS开关包括第一PMOS和NMOS耦合晶体管。 发生器经由第一和第二输出提供第一和第二电压电平，并且包括第二PMOS和NMOS晶体管。 第二PMOS晶体管串联连接在VDD和第一偏置源之间，第二NMOS晶体管串联连接在VSS和第二偏置源之间。 在其输出之间耦合到发生器的升压电路和CMOS开关的PMOS和NMOS栅极电容性地存储在耦合到PMOS和NMOS栅极的关断电平的第一和第二升压电压。 升压电压分别从VDD和VSS偏移大约相应晶体管类型的阈值电压。

公开(公告)号：US07821754B2

公开(公告)日：2010-10-26

申请号：US12063474

申请日：2006-08-11

Applicant: Mathias Krauss

Inventor： Mathias Krauss

IPC: H02H3/24

CPC classification number: G01R31/026 ,  G01D3/08 ,  H03K17/22 ,  H03K2017/6875

Abstract: A circuit arrangement for producing a defined output signal in CMOS integrated circuit is provided in which the output of a sensor signal conditioning circuit is connected to the drain terminal of a first N channel depletion transistor, to a source terminal of a second N channel depletion transistor and to the output (OUT) of an integrated CMOS circuit. The gate terminals of the first and second N channel depletion transistors are connected to the output (VP) of a control circuit and the first terminal of a discharge resistance. The second terminal of the discharge resistance and the source terminal of the first N channel depletion transistor are connected to a potential VSS, and the drain terminal of the second N channel depletion transistor is connected to a potential VDD.

Abstract translation: 提供了一种用于在CMOS集成电路中产生定义的输出信号的电路装置，其中传感器信号调节电路的输出连接到第一N沟道耗尽晶体管的漏极端，连接到第二N沟道耗尽型晶体管的源极端 以及集成CMOS电路的输出（OUT）。 第一和第二N沟道耗尽晶体管的栅极端子连接到控制电路的输出（VP）和放电电阻的第一端子。 放电电阻的第二端子和第一N沟道耗尽型晶体管的源极端子连接到电位VSS，并且第二N沟道耗尽型晶体管的漏极端子连接到电位VDD。

公开(公告)号：US07322618B2

公开(公告)日：2008-01-29

申请号：US11013757

申请日：2004-12-15

Applicant: Detlef Henrich ,  Mathias Krauss ,  Goran Lebo ,  Stephan Mann

Inventor： Detlef Henrich ,  Mathias Krauss ,  Goran Lebo ,  Stephan Mann

IPC: F16L33/00

CPC classification number: F16L33/04

Abstract: A hose coupling with a clamp which can be clamped around a longitudinal axis, wherein the edges of the clamp are located closer to the longitudinal axis than an area of the clamp located between the edges. The hose coupling further includes a pipe, wherein an end portion of the hose can be pushed onto an end portion of the pipe and can be clamped by means of the clamp. The end portion of the pipe is provided with a circumferential holding rib, wherein the end portion of the hose can be pushed past the holding rib and wherein the clamp can be clamped on the hose above the holding rib so that the hose is secured between the holding rib and the clamp. The clamp includes an elastic, circular circumferential metal clamping band of uniform thickness.

Abstract translation: 与可夹紧在纵向轴线上的夹具的软管接头，其中夹具的边缘比位于边缘之间的夹具的区域更靠近纵向轴线定位。 软管接头还包括管，其中软管的端部可以被推到管的端部上，并且可以通过夹具夹紧。 管的端部设置有周向保持肋，其中软管的端部可以被推过保持肋，并且其中夹具可以夹持在保持肋上方的软管上，使得软管固定在 握住肋骨和夹具。 夹具包括均匀厚度的弹性圆形周向金属夹紧带。

公开(公告)号：US20050172460A1

公开(公告)日：2005-08-11

申请号：US11043383

申请日：2005-01-26

Applicant: Helmut Geppert ,  Mathias Krauss

Inventor： Helmut Geppert ,  Mathias Krauss

IPC: F16L33/06 ,  A44B99/00 ,  F16L33/04 ,  F16L33/08 ,  F16L33/00

CPC classification number: F16L33/08 ,  F16L33/04 ,  Y10T24/1441 ,  Y10T24/1443 ,  Y10T24/1445 ,  Y10T24/1447

Abstract: A connection of a hose clamp and a hose has a rubber-elastic ring that surrounds the hose detachably and with elastic pretension. The ring is positioned underneath a clamp strap of the hose clamp. The ring has radial hook-shaped first projections for locking the clamp strap of the hose clamp between the first projections by engaging across edges of the clamp strap. The first projections are formed on edges of the ring. The thickness of the ring in an area located axially between the first projections is 5% to 9% of the wall thickness of the hose.

Abstract translation: 软管夹和软管的连接件具有橡胶弹性环，其可拆卸地围绕软管并具有弹性预紧力。 环位于软管夹的夹紧带的下方。 环具有径向钩状的第一突起，用于通过接合夹紧带的边缘来将软管夹的夹紧带锁定在第一突起之间。 第一突起形成在环的边缘上。 在轴向位于第一突起之间的区域中的环的厚度为软管壁厚的5％至9％。

公开(公告)号：US5602467A

公开(公告)日：1997-02-11

申请号：US392792

申请日：1995-04-24

Applicant: Mathias Krauss ,  Beate Hildebrandt ,  Christian Kunath ,  Eberhard Kurth

Inventor： Mathias Krauss ,  Beate Hildebrandt ,  Christian Kunath ,  Eberhard Kurth

IPC: G01N27/414 ,  G01N27/416 ,  G01R27/26

CPC classification number: G01N27/4148

Abstract: A circuit layout for measuring ion concentrations in solutions using ion-sitive field effect transistors is provided. The circuit layout makes it possible to represent the threshold voltage difference of two ISFETs directly and independently of technological tolerances, operationally caused parameter fluctuations, and ambient influences. The circuit layout includes two measuring or test amplifiers, with in each case two differently or identically sensitive ISFETs and two identical FETs. The ISFETs and FETs are connected in such a manner that at the output of the first measuring amplifier occurs the difference of the mean value of the two ISFET threshold voltages and the FET threshold voltage and at the output of the second measuring amplifier occurs the difference of the two ISFET threshold voltages. The output of the first amplifier is connected to the common reference electrode of the four ISFETs.

Abstract translation: PCT No.PCT / DE93 / 00690 Sec。 371日期1995年04月24日 102（e）日期1995年4月24日PCT提交1993年8月4日PCT公布。 公开号WO94 / 06005 日期1994年3月17日提供了使用离子敏感场效应晶体管测量溶液中离子浓度的电路布局。 电路布局使得可以直接和独立于工艺公差，可操作地引起参数波动和环境影响来表示两个ISFET的阈值电压差。 电路布局包括两个测量或测试放大器，每种情况下两个不同或相同的ISFET和两个相同的FET。 ISFET和FET以这样的方式连接，使得在第一测量放大器的输出处发生两个ISFET阈值电压的平均值和FET阈值电压的差异，并且在第二测量放大器的输出处的差异发生在 两个ISFET阈值电压。 第一放大器的输出连接到四个ISFET的公共参考电极。

公开(公告)号：US4879684A

公开(公告)日：1989-11-07

申请号：US168842

申请日：1988-03-16

Applicant: Mathias Krauss ,  Horst-Guenter Schniek

Inventor： Mathias Krauss ,  Horst-Guenter Schniek

IPC: G11C11/417 ,  G11C7/06 ,  G11C7/10 ,  G11C11/409

CPC classification number: G11C7/1057 ,  G11C7/062 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1096

Abstract: A read-write circuit has two data lines each of which is associated with a read circuit. The read circuit consists of three transistors connected in series, which operate in the low-signal mode in reading. By taking current from or into the bit lines according to the previously stored information the voltage ratios are changed at the outputs by which a data output driver is controlled. In writing, the n-transistors in the read circuits form with two p-transistors NOT circuits whose outputs form the data lines.

Abstract translation: 读写电路具有两条数据线，每条数据线与读取电路相关联。 读取电路由串联连接的三个晶体管组成，在读取时以低信号模式工作。 通过根据先前存储的信息从位线获取电流，在控制数据输出驱动器的输出处改变电压比。 在写入时，读取电路中的n型晶体管形成两个输出形成数据线的p型晶体管非电路。