公开(公告)号：US07068540B2

公开(公告)日：2006-06-27

申请号：US10729829

申请日：2003-12-05

申请人： Rino Micheloni ,  Roberto Ravasio

发明人： Rino Micheloni ,  Roberto Ravasio

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3454

摘要： A device and method for programming an electrically programmable memory applies at least one first programming pulse to a group of memory cells (MC1–MCk) of the memory, accesses the memory cells of the group to ascertain a programming state thereof, and applies at least one second programming pulse to those memory cells in the group whose programming state is not ascertained to correspond to a desired programming state. A voltage applied to a control electrode of the memory cells is varied between the at least one first programming pulse and the at least one second programming pulse according to a forecasted change in biasing conditions of the memory cells in the group between said at least one first and at least one second programming pulses. Undesired over-programming of the memory cells is thus avoided.

摘要翻译： 用于编程电可编程存储器的装置和方法将至少一个第一编程脉冲施加到存储器的一组存储器单元（MC 1 -MC k），访问该组的存储器单元以确定其编程状态，并应用于 至少一秒编程脉冲到组中编程状态未被确定以对应于期望的编程状态的那些存储器单元。 根据在所述至少一个第一编程脉冲和所述至少一个第二编程脉冲之间的所述组中的存储器单元的偏置条件的预测变化，施加到所述存储器单元的控制电极的电压在所述至少一个第一编程脉冲和所述至少一个第二编程脉冲之间变化 和至少一个第二编程脉冲。 因此避免了对存储器单元的不期望​​的过度编程。

公开(公告)号：US07027317B2

公开(公告)日：2006-04-11

申请号：US10720013

申请日：2003-11-20

申请人： Giovanni Campardo ,  Rino Micheloni

发明人： Giovanni Campardo ,  Rino Micheloni

IPC分类号： G11C11/24 ,  G11C14/00

CPC分类号： G11C11/005

摘要： A semiconductor memory comprises a plurality of memory cells, for example Flash memory cells, arranged in a plurality of lines, and a plurality of memory cell access signal lines, each one associated with at least one respective line of memory cells, for accessing the memory cells of the at least one respective line of memory cells; each signal line has a capacitance intrinsically associated therewith. A plurality of volatile memory cells is provided, each having a capacitive storage element. Each volatile memory cell is associated with a respective signal line, and the respective capacitive storage element formed by the capacitance intrinsically associated with the respective signal lines. In particular, the parasitic capacitances associated with bit lines of a matrix of memory cells can be exploited as capacitive storage elements.

摘要翻译： 半导体存储器包括多个存储器单元，例如布置在多个行中的闪存单元，以及多个存储单元存取信号线，每个存储单元接入信号线与至少一个相应行的存储单元相关联，用于访问存储器 存储单元的至少一个相应行的单元; 每个信号线具有与其固有相关的电容。 提供了多个易失性存储单元，每个易失性存储单元具有电容存储元件。 每个易失性存储器单元与相应的信号线相关联，并且由与各个信号线固有相关联的电容形成的相应电容存储元件。 特别地，与存储器单元的矩阵的位线相关联的寄生电容可以被用作电容性存储元件。

公开(公告)号：US07017099B2

公开(公告)日：2006-03-21

申请号：US10159782

申请日：2002-05-30

申请人： Rino Micheloni ,  Massimiliano Picca ,  Roberto Ravasio ,  Stefano Zanardi

发明人： Rino Micheloni ,  Massimiliano Picca ,  Roberto Ravasio ,  Stefano Zanardi

IPC分类号： H03M13/00

CPC分类号： G06F11/1072 ,  G11C2211/5641

摘要： A method for error control in multilevel memory cells storing a configurable number of bits. The error control is performed using an error-control code which operates, in the encoding phase, on b-bit binary strings made up of k symbols of r-bit data. When the memory cells store a number r of bits, a data symbol is formed only with the data bits stored in a memory cell. When the memory cells store a number s of bits smaller than r, a data symbol is formed with the data bits stored in a memory cell and with r-s bits having a pre-determined logic value, in which the data bits stored in the memory cell are arranged in the least significant part of the data symbol, and the r-s bits having a pre-determined logic value are arranged in the most significant part of the data symbol.

公开(公告)号：US20060023531A1

公开(公告)日：2006-02-02

申请号：US11194739

申请日：2005-08-01

申请人： Luca Crippa ,  Rino Micheloni

发明人： Luca Crippa ,  Rino Micheloni

IPC分类号： G11C7/00

CPC分类号： G11C11/5642 ,  G11C7/12 ,  G11C16/24 ,  G11C16/28

摘要： A sensing circuit is provided for sensing semiconductor memory cells. The sensing circuit includes at least one first circuit branch, a feedback-controlled circuit element in the first circuit branch, a current-to-voltage conversion circuit in the first branch, and at least one comparator. The first circuit branch is coupled to a memory cell to be sensed so as to be run through by a current corresponding to a memory cell state. The feedback-controlled circuit element controls a memory cell access voltage, and the current-to-voltage conversion circuit converts the current into a corresponding converted voltage signal that is indicative of the memory cell state. The comparator compares the converted voltage signal with a comparison voltage for discriminating among at least two different states of the memory cell. The converted voltage signal corresponds to a control signal of the feedback-controlled circuit element. Also provided is a method of sensing a memory cell.

摘要翻译： 提供感测电路用于感测半导体存储单元。 感测电路包括至少一个第一电路支路，第一电路支路中的反馈控制电路元件，第一支路中的电流 - 电压转换电路和至少一个比较器。 第一电路分支耦合到待感测的存储器单元，以便通过对应于存储单元状态的电流运行。 反馈控制电路元件控制存储单元访问电压，并且电流 - 电压转换电路将电流转换成指示存储单元状态的对应的转换电压信号。 比较器将转换的电压信号与比较电压进行比较，以便在存储单元的至少两个不同状态之间进行区分。 转换后的电压信号对应于反馈控制电路元件的控制信号。 还提供了一种感测存储器单元的方法。

公开(公告)号：US06922366B2

公开(公告)日：2005-07-26

申请号：US10423845

申请日：2003-04-24

申请人： Rino Micheloni ,  Aldo Losavio

发明人： Rino Micheloni ,  Aldo Losavio

IPC分类号： G11C29/00 ,  G11C16/04

CPC分类号： G11C29/808

摘要： A self-repair method intervenes at the end of an operation of modification of a nonvolatile memory, selected between programming and erasing, in the event of detection of just one non-functioning cell, and carries out redundancy of the non-functioning cell. To this end, the memory array is divided into a basic portion, formed by a plurality of memory cells storing basic data, and into an in-the-field redundancy portion. The in-the-field redundancy portion is designed to store redundancy data that include a correct content of the non-functioning cell, the address of the non-functioning cell, and an activated redundancy flag. The redundancy is activated only after applying a preset maximum number of modification pulses and uses a redundancy replacement circuit and a redundancy data verification circuit.

摘要翻译： 在检测到仅一个非功能单元的情况下，在编程和擦除之间选择的非易失性存储器的修改操作结束时进行自修复方法，并且执行非功能单元的冗余。 为此，存储器阵列被分成由存储基本数据的多个存储单元形成的基本部分，并且被分割成现场冗余部分。 场内冗余部分被设计为存储包括不起作用的小区的正确内容，非功能小区的地址和激活的冗余标志的冗余数据。 冗余仅在应用预设的最大数量的修改脉冲之后被激活，并且使用冗余替换电路和冗余数据验证电路。

公开(公告)号：US06901011B2

公开(公告)日：2005-05-31

申请号：US10417416

申请日：2003-04-15

申请人： Rino Micheloni ,  Aldo Losavio

发明人： Rino Micheloni ,  Aldo Losavio

IPC分类号： G06F11/10 ,  G11C16/06

CPC分类号： G06F11/1068

摘要： The method for using a nonvolatile memory (1) having a plurality of cells (14), each of which stores a datum, is based upon the steps of performing an modification operation of erasing/programming (22) the data of the memory; verifying (23) the correctness of the data of the memory cells; and, if the step of verifying (23) has revealed at least one incorrect datum, correcting on-th-field (46) the incorrect datum, using an error correcting code. The verification (23) of the correctness of the data is performed by determining (23) the number of memory cells storing an incorrect datum; if the number of memory cells storing the incorrect datum is less than or equal to a threshold (46), the erroneous datum is corrected by the error correction code; otherwise, new erasing/programming pulses are supplied.

摘要翻译： 使用具有存储数据的多个单元（14）的非易失性存储器（1）的方法基于执行擦除/编程（22）存储器的数据的修改操作的步骤; 验证（23）存储器单元的数据的正确性; 并且如果验证（23）的步骤已经透露了至少一个不正确的数据，则使用纠错码来校正不正确的数据（46）。 通过确定（23）存储不正确数据的存储单元的数量来执行数据的正确性的验证（23） 如果存储不正确的数据的存储单元的数量小于或等于阈值（46），则错误校正码校正错误的数据; 否则，将提供新的擦除/编程脉冲。

公开(公告)号：US06327184B1

公开(公告)日：2001-12-04

申请号：US09621019

申请日：2000-07-21

申请人： Rino Micheloni ,  Giovanni Campardo ,  Luca Crippa

发明人： Rino Micheloni ,  Giovanni Campardo ,  Luca Crippa

IPC分类号： G11C1606

CPC分类号： G11C16/28

摘要： The read circuit comprises an array branch having an input array node connected, via an array bit line, to an array cell; a reference branch having an input reference node connected, via a reference bit line, to a reference cell; a current-to-voltage converter connected to an output array node of the array branch and to an output reference node of the reference branch to supply on the output array node and the output reference node the respective electric potentials correlated to the currents flowing in the array memory cell and, respectively, in the reference memory cell; and a comparator connected at input to the output array node and output reference node and supplying as output a signal indicative of the contents stored in the array memory cell; and an array decoupling stage arranged between the input array node and the output array node to decouple the electric potentials of the input and output array nodes from one another.

摘要翻译： 读取电路包括具有通过阵列位线连接到阵列单元的输入阵列节点的阵列分支; 参考分支，其具有通过参考位线连接到参考单元的输入参考节点; 连接到阵列分支的输出阵列节点和参考分支的输出参考节点的电流 - 电压转换器，以在输出阵列节点和输出参考节点上提供与在 阵列存储单元，分别在参考存储单元中; 以及比较器，其输入端连接到所述输出阵列节点和输出参考节点，并且作为输出提供指示存储在所述阵列存储单元中的内容的信号; 以及布置在输入阵列节点和输出阵列节点之间的阵列解耦级，以将输入和输出阵列节点的电位彼此去耦。

公开(公告)号：US06237104B1

公开(公告)日：2001-05-22

申请号：US09222070

申请日：1998-12-29

申请人： Rino Micheloni ,  Giovanni Campardo ,  Stefano Commodaro ,  Guido Lomazzi

发明人： Rino Micheloni ,  Giovanni Campardo ,  Stefano Commodaro ,  Guido Lomazzi

IPC分类号： G06F1200

CPC分类号： G11C8/18 ,  G11C16/32

摘要： A method and related circuit for adjusting the duration of a pulse synchronization signal for the reading phase of memory cells in electronic memory devices which are integrated on semiconductors are discussed. The pulse synchronization signal is produced by a pulse generator when it detects a logical state commutation on at least one input terminal of a plurality of addressing input terminals of the memory cells. The method produces a logical sum between the signal produced by the generator and a pulse signal having a predetermined duration. The logical sum is used to start up the reading phase.

摘要翻译： 讨论了用于调整集成在半导体上的电子存储器件中的存储器单元的读取阶段的脉冲同步信号的持续时间的方法和相关电路。 当脉冲同步信号检测到存储器单元的多个寻址输入端的至少一个输入端上的逻辑状态换向时，脉冲同步信号由脉冲发生器产生。 该方法产生由发生器产生的信号与具有预定持续时间的脉冲信号之间的逻辑和。 逻辑和用于启动读取阶段。

公开(公告)号：US06181602B2

公开(公告)日：2001-01-30

申请号：US09322460

申请日：1999-05-28

申请人： Giovanni Campardo ,  Rino Micheloni ,  Alfonso Maurelli

发明人： Giovanni Campardo ,  Rino Micheloni ,  Alfonso Maurelli

IPC分类号： G11C1606

CPC分类号： G11C16/28 ,  G11C7/06 ,  G11C7/062

摘要： A method for reading memory cells that includes supplying simultaneously two memory cells, both storing a respective unknown charge condition; generating two electrical quantities, each correlated to a respective charge condition of the respective memory cell; comparing the two electrical quantities with each other; and generating a two-bit signal on the basis of the result of the comparison. A reading circuit includes a two-input comparator having two branches in parallel, each branch being connected to a respective memory cell by a current/voltage converter. Both the two-input comparator and the current/voltage converter comprise low threshold transistors.

摘要翻译： 一种用于读取存储单元的方法，包括同时提供两个存储相应未知充电条件的存储器单元; 产生两个电量，每个电量与相应存储器单元的相应充电条件相关; 将两个电量相互比较; 并根据比较结果产生2位信号。 读取电路包括并联的两个分支的双输入比较器，每个分支通过电流/电压转换器连接到相应的存储单元。 双输入比较器和电流/电压转换器均包括低阈值晶体管。

公开(公告)号：US08694849B1

公开(公告)日：2014-04-08

申请号：US13330573

申请日：2011-12-19

申请人： Rino Micheloni ,  Alessia Marelli ,  Peter Z. Onufryk

发明人： Rino Micheloni ,  Alessia Marelli ,  Peter Z. Onufryk

IPC分类号： H03M13/00

CPC分类号： H03M13/2906 ,  G06F11/1048 ,  G06F11/1076 ,  H03M13/152 ,  H03M13/19

摘要： A data storage device stores a data unit in a memory page of a storage block along with an error correction code unit for the data unit. Additionally, the data storage device stores an error correction code unit for the data unit in a memory page of another storage block. In various embodiments, one or both of the error correction code units form an error correction code for correcting data bit errors in the data unit. Because the memory page containing the data unit does not have a storage capacity for simultaneously storing the error correction code and the data unit, the data storage device is capable of correcting a greater number of data bit errors in the data unit by using the error correction code in comparison to using an error correction code that would fit in the memory page.

摘要翻译： 数据存储装置将数据单元与数据单元的纠错码单元一起存储在存储块的存储器页中。 此外，数据存储装置将用于数据单元的纠错码单元存储在另一存储块的存储器页中。 在各种实施例中，纠错码单元中的一个或两个形成用于校正数据单元中的数据位错误的纠错码。 由于包含数据单元的存储器页面不具有用于同时存储纠错码和数据单元的存储容量，所以数据存储装置能够通过使用纠错码来校正数据单元中更大数量的数据位错误 代码与使用适合内存页面的纠错码进行比较。