公开(公告)号：US06275522B1

公开(公告)日：2001-08-14

申请号：US09007390

申请日：1998-01-14

申请人： Terence Johnson ,  Michael R. May ,  Matthew A. Pendleton ,  Howard E. Levin

发明人： Terence Johnson ,  Michael R. May ,  Matthew A. Pendleton ,  Howard E. Levin

IPC分类号： H04B346

CPC分类号： H04L27/2608

摘要： In the present invention, an ADSL system (10) identifies good bin as a bin capable of successfully transmitting data to a destination. A bad bin is identified as a carrier that is not capable of successfully transmitting data to the destination. A marginal bin is identified as a carrier that may be capable of transmitting data to the destination. The power to a bad bin is reduced and allocated to the marginal or good bin(s) to allow an increased bit rate. In another embodiment, the power to marginal bin is reduced and allocated to the good bin(s).

摘要翻译： 在本发明中，ADSL系统（10）识别出能够成功地将数据发送到目的地的bin的好的bin。 一个坏的垃圾箱被识别为不能成功传送数据到目的地的载体。 边缘垃圾箱被识别为可以向目的地发送数据的载体。 减少对坏垃圾箱的电力并将其分配给边缘或好的仓，以允许增加的比特率。 在另一个实施例中，边缘垃圾箱的功率被减少并分配给好的垃圾箱。

公开(公告)号：US06100717A

公开(公告)日：2000-08-08

申请号：US174148

申请日：1998-10-16

申请人： Michael R. May

发明人： Michael R. May

IPC分类号： H04L27/00 ,  H03K19/0175

CPC分类号： H04L27/0002

摘要： A differential line driver circuit has a first operational amplifier (202) and a second operational amplifier (204). The operational amplifiers use resistors (214a, 214b, 218a, and 218b) to translate to the input voltages (206 and 208) to output voltages and VOP and VON. Feedback paths containing resistors (216a and 216b) are used to monitor output conditions whereby impedance may be actively synthesized within the operational amplifiers (202 and 204). The combination of the synthesized impedance within the operation amplifiers (202 and 204) and the physical resistance of the elements (220a and 220b) are sufficient to match the line resistance (222) of a communication line. While obtaining impedance matching in accordance with required specifications, the synthesized impedance will allow for the line driver (200) to operate with significantly reduced power consumption.

摘要翻译： 差分线路驱动器电路具有第一运算放大器（202）和第二运算放大器（204）。 运算放大器使用电阻（214a，214b，218a和218b）转换为输入电压（206和208）以输出电压和VOP和VON。 包含电阻（216a和216b）的反馈路径用于监视输出条件，从而可以在运算放大器（202和204）内主动合成阻抗。 运算放大器（202和204）内的合成阻抗和元件（220a和220b）的物理电阻的组合足以与通信线路的线路电阻（222）匹配。 在根据所需规格获得阻抗匹配的同时，合成阻抗将允许线路驱动器（200）以显着降低的功耗进行操作。

公开(公告)号：US5880687A

公开(公告)日：1999-03-09

申请号：US806271

申请日：1997-02-25

申请人： Michael R. May ,  Carlos A. Greaves

发明人： Michael R. May ,  Carlos A. Greaves

IPC分类号： H03H17/06 ,  H03M7/32 ,  H04L27/00 ,  H03M3/00

CPC分类号： H04L27/0002 ,  H03H17/0671

摘要： A cascaded integrator-comb (CIC) interpolation filter is included within a digital-to-analog converter (138) and includes two up-samplers (150, 164). The two up-samplers (150, 164) also include a sample-and-hold function. The first up-sampler (150) up-samples an output of a differentiator (140). The second up-sampler (164) up-samples an output of an integrator (152) This reduces the area and power requirements of the CIC interpolation filter, while providing approximately the same filtering performance in the pass band and transition band. The total over-sample ratio of the CIC interpolation filter is equal to the first up-sampling ratio multiplied by the second up-sampling ratio. The stop band requirements of the CIC interpolation filter determines the relative sizes of the first and second up-sampling ratios.

摘要翻译： 级联积分梳（CIC）插值滤波器包括在数模转换器（138）内，并且包括两个上采样器（150,164）。 两个上采样器（150,164）还包括采样保持功能。 第一上采样器（150）对微分器（140）的输出进行上采样。 第二个上采样器（164）对积分器（152）的输出进行上采样。这降低了CIC内插滤波器的面积和功率需求，同时在通带和过渡频带中提供了大致相同的滤波性能。 CIC内插滤波器的总超采样比等于第一个上采样比乘以第二上采样比。 CIC插值滤波器的阻带要求决定了第一和第二上采样比的相对尺寸。

公开(公告)号：US5742527A

公开(公告)日：1998-04-21

申请号：US616818

申请日：1996-03-15

申请人： Mathew A. Rybicki ,  Michael R. May ,  Matthew A. Pendleton ,  Terence L. Johnson ,  Peter R. Molnar

发明人： Mathew A. Rybicki ,  Michael R. May ,  Matthew A. Pendleton ,  Terence L. Johnson ,  Peter R. Molnar

IPC分类号： H04L25/02 ,  H04J11/00 ,  H04L25/03 ,  H04L27/26 ,  H04M11/06 ,  H04Q11/02 ,  H04Q11/04 ,  H04L5/20

CPC分类号： H04L27/2649 ,  H04Q11/0435 ,  H04Q2213/13034 ,  H04Q2213/13107 ,  H04Q2213/1313 ,  H04Q2213/1319 ,  H04Q2213/13199 ,  H04Q2213/13209 ,  H04Q2213/13376 ,  H04Q2213/13396

摘要： An ADSL receiver (200) receives an upstream modified ADSL signal and an ISDN signal from a remote terminal (32) on a twisted-pair copper wire (18). An ADSL transmitter (100) of the remote terminal (32) transmits the ADSL signal in a frequency range above an ISDN frequency range so that the ADSL signal does not overlap the frequency range of the ISDN signal. In one embodiment, the ADSL receiver (200) includes a band pass filter (201), an analog-to-digital converter (203), a decimator (205), a fast Fourier transform (210), and a digital signal processor (212). The decimator (205) converts the ADSL signal back to base band, thus allowing an ADSL signal source to simultaneously utilize the telephone line with an ISDN signal source, without significantly reducing ADSL throughput.

摘要翻译： ADSL接收机（200）从双绞铜线（18）上的远程终端（32）接收上游修改的ADSL信号和ISDN信号。 远程终端（32）的ADSL发射机（100）在ISDN频率范围之外的频率范围内发送ADSL信号，使得ADSL信号不与ISDN信号的频率范围重叠。 在一个实施例中，ADSL接收器（200）包括带通滤波器（201），模数转换器（203），抽取器（205），快速傅里叶变换（210）和数字信号处理器 212）。 抽取器（205）将ADSL信号转换回基带，从而允许ADSL信号源同时利用电话线与ISDN信号源，而不显着降低ADSL吞吐量。

公开(公告)号：US08510440B2

公开(公告)日：2013-08-13

申请号：US10226727

申请日：2002-08-22

申请人： Andrew Coleman ,  Janet E. Geddes ,  Michael R. May

发明人： Andrew Coleman ,  Janet E. Geddes ,  Michael R. May

IPC分类号： G06F15/173

CPC分类号： G06Q30/04

摘要： A method and system for assisting a user having a role and a qualification. In accordance with this method, a software tool is provided that is adapted to limit a user to a functional limitation predefined by a first role and a data access limitation predefined by a qualification. The method comprises the steps of receiving a request for assistance from said user, accessing said software tool with a customer care role having a view functionality only limitation, and simulating said first role and said qualification while operating in said customer care role, to assist said user. In the preferred embodiment, the simulation functionalities that the customer care role has, enable that customer care role to simulate update and create functionalities. Also, preferably, the customer care role may use the user's identification to obtain access to the software tool.

摘要翻译： 一种用于协助具有角色和资格的用户的方法和系统。 根据该方法，提供了一种软件工具，其适于将用户限制为由第一角色预定义的功能限制和由资格预定义的数据访问限制。 该方法包括以下步骤：从所述用户接收帮助请求，使用仅具有视图功能限制的客户关怀角色访问所述软件工具，以及在所述客户关怀角色中操作时模拟所述第一角色和所述资格，以协助所述 用户。 在优选实施例中，客户关怀角色具有的模拟功能使客户关怀角色能够模拟更新并创建功能。 此外，优选地，客户关怀角色可以使用用户的标识来获得对软件工具的访问。

公开(公告)号：US20120244825A1

公开(公告)日：2012-09-27

申请号：US13070683

申请日：2011-03-24

申请人： Brian D. Green ,  Jing Li ,  Thomas Glen Ragan ,  Michael R. May

发明人： Brian D. Green ,  Jing Li ,  Thomas Glen Ragan ,  Michael R. May

IPC分类号： H04B17/00

CPC分类号： H03G3/3073 ,  H03G3/3052 ,  H04B17/318

摘要： A radio frequency (RF) signal is received in a receiver, and various counts based on information from the signal can be obtained. Counts of a number of samples of the RF signal exceeding first and second thresholds can be accumulated during an accumulation window. From the first of these counts, it can be determined if the count exceeds a first metric corresponding to a first predetermined count value, and if so, a gain of an RF gain element can be reduced. From the second of these counts it can be determined if this count exceeds a second metric corresponding to a second predetermined count value, and if not, the gain can be increased.

摘要翻译： 在接收机中接收射频（RF）信号，并且可以获得基于来自信号的信息的各种计数。 可以在累积窗口期间累积超过第一和第二阈值的RF信号的多个样本的计数。 从这些计数中的第一个可以确定计数是否超过对应于第一预定计数值的第一度量，如果是，则可以减小RF增益元件的增益。 从这些计数中的第二个可以确定该计数是否超过对应于第二预定计数值的第二度量，如果不是，则可以增加增益。

公开(公告)号：US07940132B2

公开(公告)日：2011-05-10

申请号：US11862312

申请日：2007-09-27

申请人： Michael R. May ,  Raymond L. Vargas

发明人： Michael R. May ,  Raymond L. Vargas

IPC分类号： H03K21/10

CPC分类号： H03L7/0995 ,  G06F1/06

摘要： A clock system includes a phase locked loop, a phase divider, and a control module. The phase locked loop (PLL) produces a plurality of phase-offset output oscillations. The phase divider generates a clock signal from one or more of the plurality of phase-offset output oscillations based on a phase divider control signal. The control module generates the phase divider control signal based on a desired setting for the clock signal.

摘要翻译： 时钟系统包括锁相环，相位分配器和控制模块。 锁相环（PLL）产生多个相位偏移输出振荡。 相位分离器基于相位分配器控制信号从多个相位偏移输出振荡中的一个或多个产生时钟信号。 控制模块基于时钟信号的期望设置产生相位分配器控制信号。

公开(公告)号：US07809345B2

公开(公告)日：2010-10-05

申请号：US11796057

申请日：2007-04-26

申请人： Michael R. May

发明人： Michael R. May

IPC分类号： H04B1/06

CPC分类号： H03L7/081 ,  H03L7/089 ,  H03L7/0996 ,  H03L7/1974 ,  H03L2207/50

摘要： A digital phase locked loop (PLL) includes a digital phase detector, a digital loop filter, a digitally controlled oscillation module, and a variable feedback divider. The digital phase detector is coupled to produce a difference signal based on a phase difference between a reference oscillation and a feedback oscillation. The digital loop filter is coupled to process the difference signal to produce a control signal. The digitally controlled oscillation module is coupled to generate an output oscillation based on the control signal. The variable feedback divider is coupled to produce the feedback oscillation from the output oscillation based on a divider value and a controlled variable delay.

摘要翻译： 数字锁相环（PLL）包括数字相位检测器，数字环路滤波器，数字控制振荡模块和可变反馈分频器。 数字相位检测器被耦合以基于参考振荡和反馈振荡之间的相位差产生差分信号。 数字环路滤波器被耦合以处理差分信号以产生控制信号。 数字控制振荡模块被耦合以基于控制信号产生输出振荡。 可变反馈分压器被耦合以基于分频器值和受控变量延迟从输出振荡产生反馈振荡。

公开(公告)号：US07656968B2

公开(公告)日：2010-02-02

申请号：US11287571

申请日：2005-11-22

申请人： Erich Lowe ,  Michael R. May

发明人： Erich Lowe ,  Michael R. May

IPC分类号： H03K9/00 ,  H04L27/00

CPC分类号： H04B15/02 ,  H04B2215/065

摘要： A system on a chip integrated circuit includes an analog front end for receiving a received radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies, and for converting a selected one of the plurality of channel signals into a digital signal. A digital clock generator generates a digital clock signal at a digital clock frequency that varies based on the selected one of the plurality of channel signals. The digital clock frequency, and integer multiples of the digital clock frequency, are not substantially equal to the carrier frequency of the selected one of the plurality of channel signals. A digital section converts the digital signal into at least one audio signal that corresponds to the selected one of the plurality of channels, based on the digital clock signal.

摘要翻译： 片上集成电路系统包括：模拟前端，用于接收具有多个信道信号的接收无线电信号，多个信道信号中的每一个以对应的多个载波频率中的一个调制，并且用于将所选择的一个 的多个信道信号转换为数字信号。 数字时钟发生器以数字时钟频率产生数字时钟信号，该数字时钟频率根据所选择的多个信道信号之一而变化。 数字时钟频率和数字时钟频率的整数倍基本上不等于多个信道信号中所选择的一个的载波频率。 数字部分基于数字时钟信号将数字信号转换成对应于多个信道中所选择的一个信道的至少一个音频信号。

公开(公告)号：US07535287B2

公开(公告)日：2009-05-19

申请号：US11446612

申请日：2006-06-05

申请人： Michael R. May ,  Marcus William May

发明人： Michael R. May ,  Marcus William May

IPC分类号： G05F1/10 ,  G06F1/00

CPC分类号： H02M1/084

摘要： A system includes a first semiconductor device, a second semiconductor device, and an external crystal oscillator. The first semiconductor device includes a source voltage output and an external pin input. The first semiconductor device includes a direct current-to-direct current (DC-DC) converter circuit that provides the source voltage output. The second semiconductor device includes a source voltage input that is coupled to the source voltage output of the first semiconductor device and includes a clock signal output. The external crystal oscillator is coupled via an input of the second semiconductor device to a first oscillator clock generation circuit.

摘要翻译： 一种系统包括第一半导体器件，第二半导体器件和外部晶体振荡器。 第一半导体器件包括源极电压输出和外部引脚输入。 第一半导体器件包括提供源极电压输出的直流 - 直流（DC-DC）转换器电路。 第二半导体器件包括耦合到第一半导体器件的源极电压输出并包括时钟信号输出的源极电压输入。 外部晶体振荡器经由第二半导体器件的输入耦合到第一振荡器时钟产生电路。