公开(公告)号：US20080122106A1

公开(公告)日：2008-05-29

申请号：US11518773

申请日：2006-09-11

申请人： Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Poncth

发明人： Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Poncth

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/7682

摘要： A structure and method to produce an airgap on a substrate having a dielectric layer with a pattern transferred onto the dielectric layer and a self aligned block out mask transferred on the dielectric layer around the pattern.

摘要翻译： 在具有转印到电介质层上的图案的电介质层和在图案周围的电介质层上转移的自对准阻挡掩模的衬底上产生气隙的结构和方法。

公开(公告)号：US20120261823A1

公开(公告)日：2012-10-18

申请号：US13531518

申请日：2012-06-23

申请人： Matthew E. Colburn ,  Satya V. Nitta ,  Sampath Purushothaman ,  Charles Black ,  Kathryn Guarini

发明人： Matthew E. Colburn ,  Satya V. Nitta ,  Sampath Purushothaman ,  Charles Black ,  Kathryn Guarini

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L21/31144 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.

摘要翻译： 描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧 具有盖电介质的孔阵列的顶部。 还描述了构建多层纳米柱状互连结构的方法和方法的变化。

公开(公告)号：US08358011B1

公开(公告)日：2013-01-22

申请号：US11899842

申请日：2007-09-07

申请人： Matthew E. Colburn ,  Satya V. Nitta ,  Sampath Purushothaman ,  Charles Black ,  Kathryn Guarini

发明人： Matthew E. Colburn ,  Satya V. Nitta ,  Sampath Purushothaman ,  Charles Black ,  Kathryn Guarini

IPC分类号： H01L23/48

CPC分类号： H01L23/53295 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.

摘要翻译： 描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧 具有盖电介质的孔阵列的顶部。 还描述了构建多层纳米柱状互连结构的方法和方法的变化。

公开(公告)号：US20130009315A1

公开(公告)日：2013-01-10

申请号：US11899842

申请日：2007-09-07

申请人： Matthew E. Colburn ,  Satya V. Nitta ,  Sampath Purushothaman ,  Charles Black ,  Kathryn Guarini

发明人： Matthew E. Colburn ,  Satya V. Nitta ,  Sampath Purushothaman ,  Charles Black ,  Kathryn Guarini

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/53295 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.

摘要翻译： 描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧 具有盖电介质的孔阵列的顶部。 还描述了构建多层纳米柱状互连结构的方法和方法的变化。

公开(公告)号：US20110163446A1

公开(公告)日：2011-07-07

申请号：US12983885

申请日：2011-01-04

申请人： Satyanarayana Venkata Nitta ,  Sampath PURUSHOTHAMAN ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Ponoth

发明人： Satyanarayana Venkata Nitta ,  Sampath PURUSHOTHAMAN ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Ponoth

IPC分类号： H01L23/48

CPC分类号： H01L21/7682

摘要： A structure and method to produce an airgap on a substrate having a dielectric layer and copper interconnects with sublithographic perforations therein which are ordered throughout the wafer structure in a macro level and a micro level with no change in order orientation and the top layer of the copper interconnects are not exposed.

摘要翻译： 在具有电介质层和铜互连的衬底上产生气隙的结构和方法，其中的亚光刻穿孔在整个晶片结构中以宏观水平和微观级别排列，并且铜层的顶层 互连不暴露。

公开(公告)号：US07268432B2

公开(公告)日：2007-09-11

申请号：US10683333

申请日：2003-10-10

申请人： Matthew E. Colburn ,  Satya V. Nitta ,  Sampath Purushothaman ,  Charles Black ,  Kathryn Guarini

发明人： Matthew E. Colburn ,  Satya V. Nitta ,  Sampath Purushothaman ,  Charles Black ,  Kathryn Guarini

IPC分类号： H01L23/48

CPC分类号： H01L21/31144 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.

摘要翻译： 描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧 具有盖电介质的孔阵列的顶部。 还描述了构建多层纳米柱状互连结构的方法和方法的变化。

公开(公告)号：US08361704B2

公开(公告)日：2013-01-29

申请号：US12352051

申请日：2009-01-12

申请人： Matthew E. Colburn ,  Wai-kin Li ,  Haining S. Yang

发明人： Matthew E. Colburn ,  Wai-kin Li ,  Haining S. Yang

IPC分类号： G03F7/20

CPC分类号： G03F7/40 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

摘要： This invention provides a method for reducing tip-to-tip spacing between lines using a combination of photolithographic and copolymer self-assembling lithographic techniques. A mask layer is first formed over a substrate with a line structure. A trench opening of a width d is created in the mask layer. A layer of a self-assembling block copolymer is then applied over the mask layer. The block copolymer layer is annealed to form a single unit polymer block of a width or a diameter w which is smaller than d inside the trench opening. The single unit polymer block is selectively removed to form a single opening of a width or a diameter w inside the trench opening. An etch transfer process is performed using the single opening as a mask to form an opening in the line structure in the substrate.

摘要翻译： 本发明提供了使用光刻和共聚物自组装光刻技术的组合来减少线之间的尖端到尖端间隔的方法。 首先在具有线结构的衬底上形成掩模层。 在掩模层中形成宽度为d的沟槽开口。 然后将一层自组装嵌段共聚物施加在掩模层上。 对嵌段共聚物层进行退火以在沟槽开口内形成宽度或直径w小于d的单一单元聚合物嵌段。 选择性地去除单个单元聚合物嵌段以在沟槽开口内形成宽度或直径w的单个开口。 使用单个开口作为掩模进行蚀刻转印处理，以在基板中的线结构中形成开口。

公开(公告)号：US08137893B2

公开(公告)日：2012-03-20

申请号：US12983297

申请日：2011-01-01

申请人： Sean David Burns ,  Matthew E. Colburn ,  Steven John Holmes ,  Wu-Song Huang

发明人： Sean David Burns ,  Matthew E. Colburn ,  Steven John Holmes ,  Wu-Song Huang

IPC分类号： G03F7/00 ,  G03F7/004 ,  G03F7/40

CPC分类号： G03F7/40 ,  Y10T428/24802

摘要： A new lithographic process comprises reducing the linewidth of an image while maintaining the lithographic process window, and using this process to fabricate pitch split structures comprising nm order (e.g., about 22 nm) node semiconductor devices. The process comprises applying a lithographic resist layer on a surface of a substrate and patterning and developing the lithographic resist layer to form a nm order node image having an initial line width. Overcoating the nm order node image with an acidic polymer produces an acidic polymer coated image. Heating the acidic polymer coated image gives a heat treated coating on the image, the heating being conducted at a temperature and for a time sufficient to reduce the initial linewidth to a subsequent narrowed linewidth. Developing the heated treated coating removes it from the image resulting in a free-standing trimmed lithographic feature on the substrate. Optionally repeating the foregoing steps further reduces the linewidth of the narrowed line. The invention also comprises a product produced by this process.

摘要翻译： 新的光刻工艺包括在保持光刻工艺窗口的同时降低图像的线宽，并且使用该工艺来制造包括nm阶（例如约22nm）的节点半导体器件的间距分裂结构。 该方法包括在基片的表面上施加平版印刷抗蚀剂层，并对平版印刷抗蚀剂层进行图形化和显影，以形成具有初始线宽的nm阶节点图像。 用酸性聚合物覆盖nm阶节点图像产生酸性聚合物涂层图像。 加热酸性聚合物涂覆的图像给图像上的热处理涂层，加热在足以将初始线宽降低到随后变窄的线宽的温度和时间内进行。 显影加热处理的涂层将其从图像中去除，从而在基底上产生独立的修整光刻特征。 可选地，重复前述步骤进一步减小了变窄线的线宽。 本发明还包括通过该方法生产的产品。

公开(公告)号：US08053368B2

公开(公告)日：2011-11-08

申请号：US12055648

申请日：2008-03-26

申请人： Sean D. Burns ,  Matthew E. Colburn ,  Steven J. Holmes

发明人： Sean D. Burns ,  Matthew E. Colburn ,  Steven J. Holmes

IPC分类号： H01L21/311

CPC分类号： H01L21/0276 ,  G03F7/091 ,  G03F7/40

摘要： The present invention relates to a method for removing residues from open areas of a patterned substrate involving the steps of providing a layer of a developable anti-reflective coating (DBARC) over a substrate; providing a layer of a photoresist over said DBARC layer; pattern-wise exposing said photoresist layer and said DBARC layer to a radiation; developing said photoresist layer and said DBARC layer with a first developer to form patterned structures in said photoresist and DBARC layers; depositing a layer of a developer soluble material over said patterned structures; and removing said developer soluble material with a second developer.

摘要翻译： 本发明涉及一种用于从图案化衬底的开放区域去除残留物的方法，包括以下步骤：在衬底上提供可显影抗反射涂层（DBARC）的层; 在所述DBARC层上提供一层光致抗蚀剂; 将所述光致抗蚀剂层和所述DBARC层图案化地曝光到辐射; 用第一显影剂显影所述光致抗蚀剂层和所述DBARC层以在所述光致抗蚀剂和DBARC层中形成图案化结构; 在所述图案化结构上沉积一层显影剂可溶性材料; 并用第二显影剂除去所述显影剂可溶性材料。

公开(公告)号：US08017194B2

公开(公告)日：2011-09-13

申请号：US12015825

申请日：2008-01-17

申请人： Matthew E. Colburn ,  Gregory Breyta

发明人： Matthew E. Colburn ,  Gregory Breyta

IPC分类号： B05D3/00

CPC分类号： C09D153/00 ,  C08F255/00 ,  C08F293/005 ,  C08L51/06 ,  C08L53/00 ,  Y10T428/24612 ,  Y10T428/261 ,  Y10T428/269 ,  Y10T428/31855 ,  Y10T428/31938 ,  C08L2666/02

摘要： A structure that comprises a substrate; a cross-linked random free radical copolymer on the substrate; and a self-assembled patterned diblock copolymer film on the random copolymer; wherein the random copolymer is energy neutral with respect to each block of the diblock copolymer film. A method of making the structure is provided.

摘要翻译： 一种包括基底的结构; 基底上交联的无规自由基共聚物; 和无规共聚物上自组装图案化的二嵌段共聚物膜; 其中所述无规共聚物相对于所述二嵌段共聚物膜的每个嵌段是能量中和的。 提供了制作该结构的方法。