公开(公告)号：US09648144B2

公开(公告)日：2017-05-09

申请号：US14546213

申请日：2014-11-18

Applicant: MediaTek Inc.

Inventor： Chi-Cheng Ju ,  Chia-Yun Cheng ,  Yung-Chang Chang ,  Chih-Ming Wang

IPC: H04L29/06 ,  H03M7/30

CPC classification number: H04L69/04 ,  H03M7/3059 ,  H04L69/22

Abstract: A transmitter device includes a processing unit and a compression unit. The processing unit obtains a branch of data and partitions the branch of data into a plurality of snippets. Each snippet includes a group of data. The compression unit compresses each snippet into a plurality of packets according to value of each datum included in the corresponding snippet. The compression unit compares the value of each datum with a first threshold value to generate a first packet. The first packet includes first information indicating which data included in the corresponding snippet has the corresponding value not equal to the first threshold value. The compression unit further generates the remaining packets according to the first information.

公开(公告)号：US20170026648A1

公开(公告)日：2017-01-26

申请号：US15209774

申请日：2016-07-14

Applicant: MEDIATEK INC.

Inventor： Ming-Long Wu ,  Sheng-Jen Wang ,  Chia-Yun Cheng ,  Yu-Cheng Chu ,  Hao-Chun Chung ,  Shen-Kai Chang ,  Yung-Chang Chang

IPC: H04N19/13 ,  H04N19/44 ,  H04N19/42 ,  H04N19/176

CPC classification number: H04N19/13 ,  H04N19/46

Abstract: A hybrid video decoder has a hardware decoding circuit, a software decoding circuit, and a meta-data access system. The hardware decoding circuit deals with a first portion of a video decoding process for at least a portion of a frame, wherein the first portion of the video decoding process includes entropy decoding. The software decoding circuit deals with a second portion of the video decoding process. The meta-data access system manages meta data transferred between the hardware decoding circuit and the software decoding circuit.

Abstract translation: 混合视频解码器具有硬件解码电路，软件解码电路和元数据访问系统。 硬件解码电路处理帧的至少一部分的视频解码处理的第一部分，其中视频解码处理的第一部分包括熵解码。 软件解码电路处理视频解码过程的第二部分。 元数据访问系统管理在硬件解码电路和软件解码电路之间传送的元数据。

公开(公告)号：US20160241863A1

公开(公告)日：2016-08-18

申请号：US15028717

申请日：2015-09-17

Applicant: MEDIATEK INC.

Inventor： Ming-Long Wu ,  Chia-Yun Cheng ,  Yung-Chang Chang

IPC: H04N19/436 ,  H04N19/172 ,  H04N19/174 ,  H04N19/91 ,  H04N19/44 ,  H04N19/593 ,  H04N19/70 ,  H04N19/127 ,  H04N19/184

CPC classification number: H04N19/436 ,  H04N19/127 ,  H04N19/172 ,  H04N19/174 ,  H04N19/184 ,  H04N19/44 ,  H04N19/593 ,  H04N19/70 ,  H04N19/91

Abstract: A syntax parsing apparatus includes a plurality of syntax parsing circuits and a dispatcher. Each of the syntax parsing circuits has at least entropy decoding capability. The syntax parsing circuits generate a plurality of entropy decoding results of a plurality of image regions within a same frame, respectively. The dispatcher assigns bitstream start points of the image regions to the syntax parsing circuits, and triggers the syntax parsing circuits to start entropy decoding, respectively.

Abstract translation: 语法解析装置包括多个语法解析电路和调度器。 每个语法解析电路至少具有熵解码能力。 语法解析电路分别在同一帧内产生多个图像区域的多个熵解码结果。 调度员将图像区域的位流起始点分配给语法解析电路，并分别触发语法解析电路以开始熵解码。

公开(公告)号：US20160191935A1

公开(公告)日：2016-06-30

申请号：US14979578

申请日：2015-12-28

Applicant: MEDIATEK INC.

Inventor： Ping Chao ,  Chia-Yun Cheng ,  Chih-Ming Wang ,  Yung-Chang Chang

IPC: H04N19/423 ,  G06F5/06 ,  H04N19/44 ,  G06F12/08

CPC classification number: H04N19/423 ,  G06F5/065 ,  G06F12/0811 ,  G06F2205/067 ,  G06F2212/283 ,  H04N19/127 ,  H04N19/172 ,  H04N19/436 ,  H04N19/44

Abstract: A multi-core decoder system and an associated method use a decoding progress synchronizer to reduce bandwidth consumption for decoding a video bitstream is disclosed. In one embodiment of the present invention, the multi-core decoder system includes a shared reference data buffer coupled to the multiple decoder cores and an external memory. The shared reference data buffer stores reference data received from the external memory and provides the reference data the multiple decoder cores for decoding video data. The multi-core decoder system also includes one or more decoding progress synchronizers coupled to the multiple decoder cores to detect decoding-progress information associated with the multiple decoder cores or status information of the shared reference data buffer, and to control decoding progress for the multiple decoder cores.

Abstract translation: 公开了一种多核解码器系统和相关联的方法，使用解码进步同步器来减少用于解码视频比特流的带宽消耗。 在本发明的一个实施例中，多核解码器系统包括耦合到多个解码器核心的共享参考数据缓冲器和外部存储器。 共享参考数据缓冲器存储从外部存储器接收的参考数据，并为参考数据提供用于解码视频数据的多个解码器核心。 多核解码器系统还包括耦合到多个解码器核心的一个或多个解码进步同步器，以检测与多个解码器核心相关联的解码进度信息或共享参考数据缓冲器的状态信息，并且控制多个解码器的解码进程 解码器核心。

公开(公告)号：US20160021378A1

公开(公告)日：2016-01-21

申请号：US14767912

申请日：2015-01-21

Applicant: MEDIATEK INC.

Inventor： Chia-Yun Cheng ,  Chi-Cheng Ju ,  Yung-Chang Chang ,  Chih-Ming Wang

IPC: H04N19/176 ,  H04N19/44 ,  H04N19/60

CPC classification number: H04N19/91 ,  H04N19/129 ,  H04N19/176 ,  H04N19/18 ,  H04N19/44 ,  H04N19/463 ,  H04N19/60 ,  H04N19/70 ,  H04N19/82

Abstract: A decoding apparatus has an arithmetic decoder and a controller. A counter logic of the controller generates a first statistics result according to a first syntax element decoding result. A control logic of the controller instructs the arithmetic decoder to perform a first scan procedure at least once to generate the first syntax element decoding result of transform coefficients of a transform coefficient block, controls a repetition number of a second scan procedure based at least partly on the first statistics result, and instructs the arithmetic decoder to perform the second scan procedure at least once to generate a second syntax element decoding result of the transform coefficients. The first scan procedure decodes a first coded syntax element of one transform coefficient when performed by the arithmetic decoder once. The second scan procedure decodes a second coded syntax element of one transform coefficient when performed by the arithmetic decoder once.

Abstract translation: 解码装置具有算术解码器和控制器。 控制器的计数器逻辑根据第一语法元素解码结果产生第一统计结果。 控制器的控制逻辑指示算术解码器至少执行一次第一扫描过程以产生变换系数块的变换系数的第一语法元素解码结果，至少部分地基于第二扫描过程控制重复次数 第一统计结果，并且指示算术解码器至少执行第二扫描过程以产生变换系数的第二语法元素解码结果。 当由算术解码器执行一次时，第一扫描程序解码一个变换系数的第一编码语法元素。 当由算术解码器执行一次时，第二扫描程序解码一个变换系数的第二编码语法元素。

公开(公告)号：US20150350566A1

公开(公告)日：2015-12-03

申请号：US14722162

申请日：2015-05-27

Applicant: MEDIATEK INC.

Inventor： Meng-Jye Hu ,  Yung-Chang Chang ,  Chia-Yun Cheng

IPC: H04N5/262

CPC classification number: H04N5/2628 ,  H04N19/122 ,  H04N19/136 ,  H04N19/159 ,  H04N19/176 ,  H04N19/70

Abstract: One exemplary video processing apparatus includes a control circuit and a size selection circuit. The control circuit determines picture boundary information. The size selection circuit refers to at least the picture boundary information to select a size for a block associated with encoding of a picture, wherein selection of the size is constrained by the picture boundary information to ensure that the block with the selected size is not across a picture boundary of the picture.

Abstract translation: 一个示例性视频处理设备包括控制电路和尺寸选择电路。 控制电路确定图像边界信息。 尺寸选择电路至少指图像边界信息以选择与图像编码相关联的块的大小，其中尺寸的选择被图像边界信息约束，以确保具有所选尺寸的块不跨越 图片的图片边界。

公开(公告)号：US08990435B2

公开(公告)日：2015-03-24

申请号：US13681426

申请日：2012-11-20

Applicant: Mediatek Inc.

Inventor： Chia-Yun Cheng ,  Yung-Chang Chang

IPC: G06F3/00 ,  G06F5/00 ,  G09G5/00 ,  H04N19/129 ,  H04N19/174 ,  H04N19/176 ,  H04N19/423 ,  H04N19/436 ,  H04N19/44

CPC classification number: G11B20/10527 ,  G09G5/001 ,  G11B2020/10675 ,  H04N9/87 ,  H04N19/129 ,  H04N19/13 ,  H04N19/174 ,  H04N19/423 ,  H04N19/44 ,  H04N21/44004

Abstract: A method for read pointer maintenance of a buffering apparatus, which is arranged to buffer data of a multi-tile encoded picture having a plurality of tiles included therein, includes the following steps: judging if decoding of a first tile of the multi-tile encoded picture encounters a tile boundary of the first tile; and when it is judged that the tile boundary of the first tile is encountered, storing a currently used read pointer into a pointer buffer, and loading a selected read pointer from the pointer buffer to act as the currently used read pointer.

Abstract translation: 一种用于缓冲装置的读指针维护方法，其被设置为缓冲其中包括多个瓦片的多瓦片编码图像的数据，包括以下步骤：判断多瓦片编码的第一瓦片的解码 图片遇到第一瓦片的瓦片边界; 并且当判断遇到第一瓦片的瓦片边界时，将当前使用的读取指针存储到指针缓冲器中，并且从指针缓冲器加载所选择的读取指针以充当当前使用的读取指针。

公开(公告)号：US12143612B2

公开(公告)日：2024-11-12

申请号：US17855829

申请日：2022-07-01

Applicant: MEDIATEK INC.

Inventor： Sheng-Jen Wang ,  Chao-I Wu ,  Ming-Long Wu ,  Chia-Yun Cheng

IPC: H04N19/00 ,  H04N19/13 ,  H04N19/423 ,  H04N19/44

Abstract: A context-based adaptive binary arithmetic coding (CABAC) decoder includes a bin decode circuit and a context update circuit. The bin decode circuit supports decoding of multiple bins in one cycle. The multiple bins include a first bin and a second bin. The bin decode circuit generates a bin value of the first bin according to a first set of multiple contexts, a first range and a first offset, and generates one bin value of the second bin according to a second set of multiple contexts, a second range and a second offset. The context update circuit updates the first set of multiple contexts in response to the bin value of the first bin, to generate a first set of multiple updated contexts, and updates the second set of multiple contexts in response to said one bin value of the second bin, to generate a second set of multiple updated contexts.

公开(公告)号：US10771163B2

公开(公告)日：2020-09-08

申请号：US16163581

申请日：2018-10-18

Applicant: MEDIATEK INC.

Inventor： Min-Hao Chiu ,  Chia-Yun Cheng ,  Yung-Chang Chang

IPC: H04B10/69 ,  H04N19/70 ,  H04N19/184 ,  G06T9/00 ,  H04N19/127 ,  H04N19/44 ,  H04N19/42 ,  H04N19/17

Abstract: A decoding apparatus is used for decoding region of interest (ROI) regions in an image, and includes a storage device, a pre-processing circuit, a decoding circuit, and an information fetching circuit. The pre-processing circuit performs a syntax pre-parsing operation upon a bitstream to obtain necessary information of the ROI regions, and stores the necessary information into the storage device. The decoding circuit performs a decoding operation upon the bitstream to decode the ROI regions, wherein the decoding operation includes syntax parsing of the bitstream. The information fetching circuit reads and analyzes the necessary information, and delivers at least a portion of the necessary information to the decoding circuit. A processing time of obtaining necessary information of one ROI region at the pre-processing circuit overlaps a processing time of decoding another ROI region at the decoding circuit.

公开(公告)号：US20200177909A1

公开(公告)日：2020-06-04

申请号：US16697119

申请日：2019-11-26

Applicant: MEDIATEK INC.

Inventor： Yung-Chang Chang ,  Chia-Yun Cheng ,  Cheng-Han Li ,  Hong-Cheng Lin ,  Chi-Hung Chen

IPC: H04N19/52 ,  H04N19/176 ,  H04N19/119

Abstract: A motion vector (MV) projection method includes generating motion field motion vectors (MFMVs) for a first portion of a current frame by applying MV projection to MVs of a portion of each of reference frames and storing the MFMVs of the first portion of the current frame into an MFMV buffer, and generating MFMVs for a second portion of the current frame by applying MV projection to MVs of a portion of each of the reference frames and storing the MFMVs of the second portion of the current frame into the MFMV buffer. The second portion does not overlap the first portion. Before generating the MFMVs for the second portion of the current frame is done, at least one of the MFMVs of the first portion is read from the MFMV buffer and involved in motion vector determination of at least one coding block included in the first portion.