公开(公告)号：US20230050155A1

公开(公告)日：2023-02-16

申请号：US17402545

申请日：2021-08-15

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gil Levy ,  Aviv Kfir ,  Pedro Reviriego ,  Salvatore Pontarelli

IPC: H04L29/06

Abstract: A network element includes one or more ports and a packet processor. The one or more ports are to transmit and receive packets over a network. The packet processor is to apply a plurality of rules to the packets, each rule specifying (i) expected values for each header field of a group of header fields of the packets, including, for a given header field in the group, at least a set of multiple expected values, (ii) a group ID associated with the set, and (iii) an action to be applied to the packets whose header fields match the expected values.

公开(公告)号：US20250039109A1

公开(公告)日：2025-01-30

申请号：US18225562

申请日：2023-07-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Eran Gil Beracha ,  Liron Mula ,  Barak Gafni ,  Gil Levy ,  Aviv Kfir

IPC: H04L49/9047 ,  H04L47/125 ,  H04L47/62

Abstract: A system, a computing system, and a switch are provided. In one example, a system for routing data to one of a plurality of queues comprises a processor to poll a depth of one or more queues of the plurality of queues, determine a weight for each polled queue based on the depth of each polled queue, and route data received via a port to a first queue of the plurality of queues based on the determined weight for each polled queue.

公开(公告)号：US11968285B2

公开(公告)日：2024-04-23

申请号：US17679160

申请日：2022-02-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gil Levy ,  Aviv Kfir

IPC: H04L69/22 ,  H03M7/30 ,  H04L45/74 ,  H04L45/745

CPC classification number: H04L69/22 ,  H03M7/3082 ,  H04L45/742 ,  H04L45/74591

Abstract: A network device includes one or more ports, and action-select circuitry. The ports are to exchange packets over a network. The act-ion-select circuitry is to determine, for a given packet, a first search key based on a first header field of the given packet, and a second search key based on a second header field of the given packet, to compare the first search key to a first group of compare values, to output a multi-element vector responsively to a match between the first search key and a first compare value, to generate a composite search key by concatenating the second search key and the multi-element vector, to compare the composite search key to a second group of compare values, and, responsively to a match between the composite search key and a second compare value, to output an action indicator for applying to the given packet.

公开(公告)号：US11929837B2

公开(公告)日：2024-03-12

申请号：US17678074

申请日：2022-02-23

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gil Levy ,  Roni Bar Yanai ,  Avi Urman

IPC: G06F16/22 ,  G06F16/28 ,  H04L1/20

CPC classification number: H04L1/201 ,  G06F16/2255 ,  G06F16/285

Abstract: A classification apparatus includes a memory and a processor. The memory is configured to store rules corresponding to a corpus of rules in respective rule entries, each rule includes a respective set of unmasked bits having corresponding bit values, and at least some of the rules include masked bits. The rules in the corpus conform to respective Rule Patterns (RPs), each RP defining a respective sequence of masked and unmasked bits. The processor is configured to cluster the RPs, using a clustering criterion, into extended Rule Patterns (eRPs) associated with respective hash tables including buckets for storing rule entries. The clustering criterion aims to minimize an overall number of the eRPs while meeting a collision condition that depends on a specified maximal number of rule entries per bucket.

公开(公告)号：US20230353664A1

公开(公告)日：2023-11-02

申请号：US18314834

申请日：2023-05-10

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gil Levy ,  Liron Mula ,  Barak Gafni

IPC: H04L69/22 ,  H04L69/324 ,  H04L69/323

CPC classification number: H04L69/22 ,  H04L69/324 ,  H04L69/323

Abstract: A parsing apparatus includes a packet-type identification circuit and a parser. The packet-type identification circuit is to receive a packet to be parsed, and to identify a packet type of the packet by extracting a packet-type identifier from a defined field in the packet. The parser is to store one or more parsing templates that specify parsing of one or more respective packet types. When the packet type of the packet corresponds to a parsing template among the stored parsing templates, the parser is to parse the packet in accordance with the stored parsing template. When the packet type of the packet does not correspond to any of the stored parsing templates, the parser is to parse the packet using an alternative parsing scheme.

公开(公告)号：US11656958B2

公开(公告)日：2023-05-23

申请号：US17244539

申请日：2021-04-29

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Liron Mula ,  Gil Levy ,  Itamar Rabenstein

IPC: G06F11/20 ,  G06F9/50 ,  G06F13/20

CPC classification number: G06F11/2007 ,  G06F9/5011 ,  G06F13/20 ,  G06F2201/85

Abstract: Methods, systems, and devices for redundant data bus inversion (DBI) sharing are described. A device may identify a group of channels included in a data bus. The device may determine whether the group of channels satisfies a criterion. Based on the determination, the device may allocate an overhead channel to the group of channels for a set of redundancy operations. Based on the determination, the device may allocate the overhead channel to the group of channels for a set of data bus inversion operations. The device may encode data associated with the group of channels based on the allocation of the overhead channel. The overhead channel may be included in the data bus.

公开(公告)号：US20230138522A1

公开(公告)日：2023-05-04

申请号：US17516731

申请日：2021-11-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Niv Aibester ,  Barak Gafni ,  Aviv Kfir ,  Gil Levy

IPC: G06F3/06

Abstract: A network device includes a memory and a memory management circuit. The memory is to store a shared buffer. The memory management circuit is to estimate respective bandwidth measures for one or more queues used in processing packets in the network device, and to allocate and deallocate segments of the shared buffer to at least one of the queues based on the bandwidth measures.

公开(公告)号：US20230074989A1

公开(公告)日：2023-03-09

申请号：US17987911

申请日：2022-11-16

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Yamin Friedman ,  Daniel Marcovitch ,  Gil Levy

IPC: H04L47/34 ,  H04L1/18

Abstract: In one embodiment, a communication apparatus, including a network interface configured to receive over a network a sequence of data packets of a network flow having a defined packet order, wherein the network interface is configured to receive an out-of-order data packet instead of multiple missing data packets according to the defined packet order, a timer, and packet processing circuitry configured to activate the timer responsively to receiving the out-of-order data packet, and set the time period over which the tinier is activated responsively to a quantity of the multiple missing data packets.

公开(公告)号：US20230022037A1

公开(公告)日：2023-01-26

申请号：US17955591

申请日：2022-09-29

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Niv Aibester ,  Aviv Kfir ,  Gil Levy ,  Liron Mula ,  Barak Gafni

IPC: H04L49/90 ,  H04L43/0876 ,  H04L47/6275

Abstract: An apparatus for controlling a Shared Buffer (SB), the apparatus including an interface and a SB controller. The interface is to access flow-based data counts and admission states. The SB controller is to perform flow-based accounting of packets received by a network device coupled to a communication network, for producing flow-based data counts, each flow-based data count associated with one or more respective flows, and to generate admission states based at least on the flow-based data counts, each admission state being generated from one or more respective flow-based data counts.

公开(公告)号：US20190173776A1

公开(公告)日：2019-06-06

申请号：US15831414

申请日：2017-12-05

Applicant: Mellanox Technologies, Ltd.

Inventor： Gil Levy ,  Alex Shpiner ,  Benny Koren

IPC: H04L12/707 ,  H04L12/803 ,  H04L12/801 ,  H04L12/833

Abstract: A network element includes multiple ports and packet processing circuitry. The ports are configured for exchanging packets with a communication network. The packet processing circuitry is configured to forward first packets over a forward path from a source node to a destination node, to forward second packets over a reverse path, which is opposite in direction to the forward path, from the destination node to the source node, and to mark one or more of the second packets that are forwarded over the reverse path, with an indication that notifies the source node that congestion is present on the forward path.