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    Hardware Clock with Built-In Accuracy Check
    21.
    发明申请
    Hardware Clock with Built-In Accuracy Check 有权

    公开(公告)号：US20220224500A1

    公开(公告)日：2022-07-14

    申请号：US17148605

    申请日：2021-01-14

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Liron Mula ,  Dotan David Levi ,  Ariel Almog

    IPC: H04L7/00

    Abstract: A network device includes one or more ports for connecting to a communication network, packet processing circuitry and clock circuitry. The packet processing circuitry is configured to communicate packets over the communication network via the ports. The clock circuitry includes a hardware clock configured to indicate a network time used for synchronizing network devices in the communication network, and a built-in accuracy test circuit configured to check an accuracy of the hardware clock.

    Explicit notification of operative conditions along a network path
    22.
    发明申请
    Explicit notification of operative conditions along a network path 有权

    公开(公告)号：US20210344782A1

    公开(公告)日：2021-11-04

    申请号：US17198292

    申请日：2021-03-11

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Yuval Shpigelman ,  Idan Burstein ,  Aviv Kfir ,  Liron Mula ,  Niv Aibester ,  Gil Levy

    IPC: H04L29/06 ,  H04L12/801 ,  H04L1/00

    Abstract: A network element includes circuitry and multiple ports. The multiple ports are configured to connect to a communication network. The circuitry is configured to receive via one of the ports a packet that originated from a source node and is destined to a destination node, the packet including a mark that is indicative of a cumulative state derived from at least bandwidth utilization conditions of output ports that were traversed by the packet along a path, from the source node up to the network element, to select a port for forwarding the packet toward the destination node, to update the mark of the packet based at least on a value of the mark in the received packet and on a local bandwidth utilization condition of the selected port, and to transmit the packet having the updated mark to the destination node via the selected port.

    Network Adapter with Time-Aware Packet-Processing Pipeline
    24.
    发明申请
    Network Adapter with Time-Aware Packet-Processing Pipeline 有权

    公开(公告)号：US20210243140A1

    公开(公告)日：2021-08-05

    申请号：US16782075

    申请日：2020-02-05

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Dotan David Levi ,  Avi Urman ,  Lior Narkis ,  Liron Mula

    IPC: H04L12/861 ,  H04L29/06 ,  H04L12/741 ,  H04L12/46 ,  H04L12/931 ,  H04L12/801 ,  H04W56/00

    Abstract: A network adapter includes a host interface configured to communicate with a host, a network interface configured to communicate with a communication network, and packet processing circuitry. The packet processing circuitry is configured to receive a packet from the host via the host interface, or from the communication network via the network interface, to receive an indication of a network time used for synchronizing network elements in the communication network, to match the packet to a rule, the rule including a condition and an action, and to perform the action in response to the packet meeting the condition, wherein one or more of (i) the condition in the rule and (ii) the action in the rule, depend on the network time.

    POWER-OPTIMIZED AND SHARED BUFFER
    26.
    发明申请
    POWER-OPTIMIZED AND SHARED BUFFER 有权

    公开(公告)号：US20250044981A1

    公开(公告)日：2025-02-06

    申请号：US18229509

    申请日：2023-08-02

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Niv Aibester ,  Eyal Srebro ,  Liron Mula ,  Amit Kazimirsky

    IPC: G06F3/06

    Abstract: A network device, a network interface controller, and a switch are provided. In one example, a shared buffer includes a plurality of cells of memory, one or more ports read data from the shared buffer and write data to the shared buffer, and a controller circuit selectively enables and disables cells of memory of the shared buffer based on an amount of data stored in the shared buffer. Power consumption of the shared buffer is in proportion to a number of enabled cells of memory.

    BI-DIRECTIONAL ENCRYPTION/DECRYPTION DEVICE FOR UNDERLAY AND OVERLAY OPERATIONS
    27.
    发明公开
    BI-DIRECTIONAL ENCRYPTION/DECRYPTION DEVICE FOR UNDERLAY AND OVERLAY OPERATIONS 审中-公开

    公开(公告)号：US20240236059A1

    公开(公告)日：2024-07-11

    申请号：US18615674

    申请日：2024-03-25

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Barak Gafni ,  Liron Mula

    IPC: H04L9/40 ,  H04L12/46

    CPC classification number: H04L63/0485 ,  H04L63/162 ,  H04L63/164 ,  H04L12/4633 ,  H04L63/0428

    Abstract: Technologies for bi-directional encryption and decryption for underlay and overlay operations are described. One network device a path-selection circuit that operates in a first mode or a second mode. In the first mode, the path-selection circuit receives a first incoming packet on a first port, sends it to a security circuitry to decrypt the first incoming packet to obtain a first decrypted packet, sends the first decrypted packet to a processing circuitry to process the first decrypted packet to obtain a first outgoing packet, and sends the first outgoing packet to a second port of the network device. In the second mode, the path-selection circuit receives a second incoming packet on a third port, sends it to the processing circuitry to de-encapsulate the second incoming packet to obtain a second outgoing packet, and sends the second outgoing packet to a fourth port of the network device.

    Ethernet pause aggregation for a relay device
    30.
    发明授权
    Ethernet pause aggregation for a relay device 有权

    公开(公告)号：US11888753B2

    公开(公告)日：2024-01-30

    申请号：US17398677

    申请日：2021-08-10

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Liron Mula ,  Zachy Haramaty ,  Shachar Bar Tikva ,  Dekel Dadon

    IPC: H04L12/823 ,  H04L47/32 ,  H04L47/30

    CPC classification number: H04L47/32 ,  H04L47/30

    Abstract: A relay device is provided that may identify a quantity of empty data byte locations in a data buffer of the relay device. The relay device may receive an indicator associated with transmitting data packets. The relay device may pause or enable a lossless flow of data between the relay device, a host device, and a peer device based on the quantity of empty data byte locations, the indicator, or both. The relay device may include a first data interface coupled with a peer device, a second data interface coupled with a host device, a data buffer configured to store data packets received from the host device, and a state machine that enables a lossless transmission of data between the host device and peer device. The state machine may transmit a pause frame to the host device based on a data buffer utilization reaching a data storage capacity.

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