利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

136 条记录 (耗时 0.025 秒)

    Techniques to control access to logic
    21.
    发明申请
    Techniques to control access to logic 失效
    控制逻辑访问的技术

    公开(公告)号：US20050238019A1

    公开(公告)日：2005-10-27

    申请号：US11170294

    申请日：2005-06-28

    申请人： Anil Vasudevan ,  Sujoy Sen ,  Nimrod Diamant

    发明人： Anil Vasudevan ,  Sujoy Sen ,  Nimrod Diamant

    IPC分类号： G06F13/28 ,  G06F15/173 ,  H01L29/40 ,  H04L12/56 ,  H04L29/06

    CPC分类号： H04L49/9042 ,  H04L47/50 ,  H04L49/90 ,  H04L69/16 ,  H04L69/161 ,  H04L69/163

    摘要： Techniques are described herein that can be used to control which packets or other data are able to be processed or otherwise utilize logic of a computing device. For example, a signature may be associated with a packet or other data received from a network. The signature and the packet or other data may be transferred to the computing device. Prior to the computing device deciding whether to allow logic such as hardware or software to use, process, or act using the packet or other data, the computing device may inspect the signature to determine if such signature permits such packet or other data to be used, processed, or acted upon.

    摘要翻译： 本文描述了可用于控制哪些分组或其他数据能够被处理或以其他方式利用计算设备的逻辑的技术。 例如，签名可以与从网络接收的分组或其他数据相关联。 签名和分组或其他数据可以被传送到计算设备。 在计算设备决定是否允许诸如硬件或软件的逻辑使用，处理或使用分组或其他数据的操作之前，计算设备可以检查签名以确定这样的签名是否允许使用这样的分组或其他数据 ，处理或采取行动。

    System and method for providing security mechanisms for securing network communication
    22.
    发明授权
    System and method for providing security mechanisms for securing network communication 有权
    提供用于保护网络通信的安全机制的系统和方法

    公开(公告)号：US06915431B1

    公开(公告)日：2005-07-05

    申请号：US09472314

    申请日：1999-12-22

    申请人： Anil Vasudevan ,  Baiju Patel ,  Marc Jalfon

    发明人： Anil Vasudevan ,  Baiju Patel ,  Marc Jalfon

    IPC分类号： G06F11/30 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177 ,  H04L9/00 ,  H04L29/06

    CPC分类号： H04L63/0428 ,  H04L63/06

    摘要： A system and method of providing security mechanisms for securing traffic communicated from a server system to a client system independent of the state of the client system. The server system determines whether the client system has entered an operational state. When the client system is operational, key exchange processes are initiated between the two systems, the results of the key exchange processes being the parameters for use in securing traffic communication between the two systems. The results are stored in the client system. The results are inhibited from being updated in the client system until the server system is successful in completely executing another set of key exchange processes. The results are updated with the results obtained from successful execution of the other set of key exchange processes if the execution of the other set is successful. The traffic communication is thus secured based on whatever results are stored in the client system.

    摘要翻译： 一种提供安全机制的系统和方法，用于保护从服务器系统传递到客户机系统的流量，而与客户端系统的状态无关。 服务器系统确定客户端系统是否已进入运行状态。 当客户端系统运行时，在两个系统之间启动密钥交换过程，密钥交换过程的结果是用于保护两个系统之间的流量通信的参数。 结果存储在客户端系统中。 在客户端系统中禁止结果被更新，直到服务器系统成功完成另一组密钥交换过程。 如果另一组的执行成功，结果将更新成功执行另一组密钥交换过程的结果。 因此，基于客户端系统中存储的任何结果来确保流量通信。

    EFFICIENT RECEIVE INTERRUPT SIGNALING
    24.
    发明申请
    EFFICIENT RECEIVE INTERRUPT SIGNALING 审中-公开

    公开(公告)号：US20200183732A1

    公开(公告)日：2020-06-11

    申请号：US16710556

    申请日：2019-12-11

    申请人： Linden Cornett ,  Anil Vasudevan ,  Parthasarathy Sarangam ,  Kiran Patil

    发明人： Linden Cornett ,  Anil Vasudevan ,  Parthasarathy Sarangam ,  Kiran Patil

    IPC分类号： G06F9/48 ,  G06F9/50

    摘要： Methods for performing efficient receive interrupt signaling and associated apparatus, computing platform, software, and firmware. Receive (RX) queues in which descriptors associated with packets are enqueued are implemented in host memory and logically partitioned into pools, with each RX queue pool associated with a respective interrupt vector. Receive event queues (REQs) associated with respective RX queue pools and interrupt vectors are also implemented in host memory. Event generation is selectively enabled for some RX queues, while event generation is masked for others. In response to event causes for RX queues that are event generation-enabled, associated events are generated and enqueued in the REQs and interrupts on associated interrupt vectors are asserted. The events are serviced by accessing the events in the REQs, which identify the RX queue for the event and a next activity location at which a next descriptor to be processed is located. After asserting an interrupt, an RX queue may be auto-masked to prevent generation of additional events when new descriptors are enqueued in the RX queue.

    Server including switch circuitry
    25.
    发明授权
    Server including switch circuitry 有权

    公开(公告)号：US09736011B2

    公开(公告)日：2017-08-15

    申请号：US13995231

    申请日：2011-12-01

    申请人： Anil Vasudevan ,  Parthasarathy Sarangam ,  Ilango S. Ganga

    发明人： Anil Vasudevan ,  Parthasarathy Sarangam ,  Ilango S. Ganga

    IPC分类号： G06F15/167 ,  H04L12/24 ,  G06F13/38

    CPC分类号： H04L41/04 ,  G06F13/385

    摘要： An embodiment may include at least one server processor that may control, at least in part, server switch circuitry data and control plane processing. The at least one processor may include at least one cache memory that is capable of being involved in at least one data transfer that involves at least one component of the server. The at least one data transfer may be carried out in a manner that by-passes involvement of server system memory. The switch circuitry may be communicatively coupled to the at least one processor and to at least one node via communication links. The at least one processor may select, at least in part, at least one communication protocol to be used by the links. The switch circuitry may forward, at least in part, via at least one of the links at least one received packet. Many modifications are possible.

    Network device selection
    26.
    发明授权
    Network device selection 有权
    网络设备选择

    公开(公告)号：US09331935B2

    公开(公告)日：2016-05-03

    申请号：US13995241

    申请日：2011-11-22

    申请人： Anil Vasudevan

    发明人： Anil Vasudevan

    IPC分类号： H04L12/775 ,  H04L12/931 ,  H04L12/947

    CPC分类号： H04L45/58 ,  H04L49/25 ,  H04L49/351 ,  H04L49/70

    摘要： An embodiment may include circuitry that may be capable of selecting, from network devices, at least one network device to which at least one packet is to be transmitted. The network devices may be associated, at least in part, with each other in at least one link aggregation. The circuitry may select the at least one network device based at least in part upon a relative degree of affinity that the at least one network device may have with respect to at least one central processing unit (CPU) socket that may be associated, at least in part, with at least one flow to which the at least one packet may belong. The relative degree of affinity may be relative to respective degrees of affinity that one or more others of the network devices may have with respect to the at least one CPU socket. Many modifications are possible.

    摘要翻译： 实施例可以包括可以能够从网络设备选择要发送至少一个分组的至少一个网络设备的电路。 网络设备至少部分地可以在至少一个链路聚合中彼此相关联。 该电路可以至少部分地基于至少一个网络设备可能相对于至少一个中央处理单元（CPU）插座具有的至少一个中心处理单元（CPU）插座的相对程度来选择该至少一个网络设备，至少一个中央处理单元 部分地与至少一个分组可以属于的至少一个流。 亲和度的相对程度可以相对于网络设备中的一个或多个其他网络设备相对于至少一个CPU插座可能具有的相对程度的亲和度。 许多修改是可能的。

    ETHERNET ENHANCEMENTS
    28.
    发明申请
    ETHERNET ENHANCEMENTS 审中-公开
    以太网增强

    公开(公告)号：US20150117177A1

    公开(公告)日：2015-04-30

    申请号：US14496667

    申请日：2014-09-25

    申请人： Ilango Ganga ,  Alain Gravel ,  Thomas Lovett ,  Radia Perlman ,  Greg Regnier ,  Anil Vasudevan ,  Hugh Wilkinson

    发明人： Ilango Ganga ,  Alain Gravel ,  Thomas Lovett ,  Radia Perlman ,  Greg Regnier ,  Anil Vasudevan ,  Hugh Wilkinson

    IPC分类号： H04L12/939 ,  H04L12/861 ,  H04L1/16

    CPC分类号： H04L49/552 ,  H04L1/1621 ,  H04L49/251 ,  H04L49/9057

    摘要： This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fibre Channel and/or other proprietary technologies, etc.

    摘要翻译： 本公开描述了对以太网的增强功能，用于诸如Storage，HPC和以太网的架构互连之类的更高性能应用。 本公开提供了用于具有错误检测和重传的无损结构增强的各种机制，以改善链路可靠性，帧优先级以允许在较低优先级业务上的较高优先级业务，通过增强IEEE802.11定义的服务功能类别来提供对死锁避免的虚拟信道支持 Q，用于架构互连中的高效转发/路由的新标题格式，以及用于结构互连中可靠的直通转发的报头CRC。 此处描述的增强功能在添加到标准和/或专有以太网协议时，将以太网适用于当前由诸如Infiniband，光纤通道和/或其他专有技术之类的备用架构技术所服务的较新的使用模式和架构互连。

    Adaptive Queuing of a Cache for a Processing Element
    29.
    发明申请
    Adaptive Queuing of a Cache for a Processing Element 有权
    处理元素缓存的自适应队列

    公开(公告)号：US20130262718A1

    公开(公告)日：2013-10-03

    申请号：US13436337

    申请日：2012-03-30

    申请人： Anil Vasudevan ,  Glenn J. Hinton ,  Yadong Li

    发明人： Anil Vasudevan ,  Glenn J. Hinton ,  Yadong Li

    IPC分类号： G06F3/00

    CPC分类号： G06F12/084 ,  G06F5/10 ,  H04L49/90

    摘要： Examples are disclosed for establishing a window for a queue structure maintained in a cache for a processing element for a network device. The processing element may be configured to operate in cooperation with an input/output device such as a network interface card. In some of these examples, the window may include portions of the queue structure having identifiers to active allocated buffers maintained in memory for the network device. The active allocated buffers may be configured to maintain or store data received or to be forwarded by the input/output device. For these examples, the window may be adjusted based on information gathered while the identifiers are read from or written to the portions of the queue structure.

    摘要翻译： 公开了用于建立用于网络设备的处理元件的高速缓存中维护的队列结构的窗口的示例。 处理元件可以被配置为与诸如网络接口卡的输入/输出设备协作操作。 在这些示例中的一些示例中，窗口可以包括具有对于网络设备的存储器中维护的主动分配缓冲区的标识符的队列结构的部分。 活动分配的缓冲器可以被配置为维护或存储由输入/输出设备接收或要转发的数据。 对于这些示例，可以基于从标识符从队列结构的部分读取或写入标识符时收集的信息来调整窗口。