公开(公告)号：US20100148259A1

公开(公告)日：2010-06-17

申请号：US12709873

申请日：2010-02-22

申请人： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

发明人： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

IPC分类号： H01L27/12 ,  H01L29/78

CPC分类号： H01L29/0653 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried insulator layer at a first depth (i.e., measured from the planar upper surface of the SOI substrate), and (3) third regions that contain second portions of the patterned buried insulator layer at a second depth, where the first depth is larger than the second depth. One or more field effect transistors (FETs) can be formed in the SOI substrate. For example, the FETs may comprise: channel regions in the first regions of the SOI substrate, source and drain regions in the second regions of the SOI substrate, and source/drain extension regions in the third regions of the SOI substrate.

摘要翻译： 提供了一种改进的绝缘体上半导体（SOI）衬底，其包含在不同深度处的图案化掩埋绝缘体层。 具体而言，SOI衬底具有基本平坦的上表面，并且包括：（1）不包含任何埋入绝缘体的第一区域，（2）第一区域，其包含第一深度处的图案化掩埋绝缘体层的第一部分 从SOI衬底的平坦的上表面），和（3）第二深度大于第二深度的第二深度上包含图案化的掩埋绝缘体层的第二部分的第三区域。 可以在SOI衬底中形成一个或多个场效应晶体管（FET）。 例如，FET可以包括：SOI衬底的第一区域中的沟道区域，SOI衬底的第二区域中的源极和漏极区域以及SOI衬底的第三区域中的源极/漏极延伸区域。

公开(公告)号：US20080128797A1

公开(公告)日：2008-06-05

申请号：US11565136

申请日：2006-11-30

申请人： Thomas W. Dyer ,  Haining S. Yang

发明人： Thomas W. Dyer ,  Haining S. Yang

IPC分类号： H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： Multiple finFETs containing semiconductor fins with the same height for the top but with different heights for the bottom are formed. Patterned oxygen implant masks are used to form a buried oxide layer with at least two different levels of oxide top surface. After the formation of the buried oxide layer, the top semiconductor layer has a substantially level top surface. Fins are formed by lithographically patterning and etching the top semiconductor layer. The resulting fins may be semiconductor fins with different heights or fins comprising an upper portion of semiconductor fins and a lower portion of oxide fins. In both cases, semiconductor fins of different heights are used to form finFETs with fractional on-current of a full height finFET.

摘要翻译： 形成了具有顶部相同高度但底部具有不同高度的半导体鳍片的多个finFET。 图案化的氧注入掩模用于形成具有至少两个不同水平的氧化物顶表面的掩埋氧化物层。 在形成掩埋氧化物层之后，顶部半导体层具有基本水平的顶表面。 通过光刻图案化和蚀刻顶部半导体层形成翅片。 所得到的翅片可以是具有不同高度或半翅片的半导体翅片，其包括半导体鳍片的上部和氧化物翅片的下部。 在这两种情况下，使用不同高度的半导体鳍形成具有全高度finFET的分数导通电流的finFET。

公开(公告)号：US07666721B2

公开(公告)日：2010-02-23

申请号：US11308292

申请日：2006-03-15

申请人： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

发明人： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

IPC分类号： H01L21/00

CPC分类号： H01L29/0653 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried insulator layer at a first depth (i.e., measured from the planar upper surface of the SOI substrate), and (3) third regions that contain second portions of the patterned buried insulator layer at a second depth, where the first depth is larger than the second depth. One or more field effect transistors (FETs) can be formed in the SOI substrate. For example, the FETs may comprise: channel regions in the first regions of the SOI substrate, source and drain regions in the second regions of the SOI substrate, and source/drain extension regions in the third regions of the SOI substrate.

摘要翻译： 提供了一种改进的绝缘体上半导体（SOI）衬底，其包含在不同深度处的图案化掩埋绝缘体层。 具体而言，SOI衬底具有基本平坦的上表面，并且包括：（1）不包含任何埋入绝缘体的第一区域，（2）第一区域，其包含第一深度处的图案化掩埋绝缘体层的第一部分 从SOI衬底的平坦的上表面），和（3）第二深度大于第二深度的第二深度上包含图案化的掩埋绝缘体层的第二部分的第三区域。 可以在SOI衬底中形成一个或多个场效应晶体管（FET）。 例如，FET可以包括：SOI衬底的第一区域中的沟道区域，SOI衬底的第二区域中的源极和漏极区域以及SOI衬底的第三区域中的源极/漏极延伸区域。

公开(公告)号：US07635899B2

公开(公告)日：2009-12-22

申请号：US11622057

申请日：2007-01-11

申请人： Haining S. Yang ,  Thomas W. Dyer ,  William C. Wille

发明人： Haining S. Yang ,  Thomas W. Dyer ,  William C. Wille

IPC分类号： H01L27/092

CPC分类号： H01L21/823878 ,  H01L21/76227 ,  H01L21/76237

摘要： A method is disclosed for forming an STI (shallow trench isolation) in a substrate during CMOS (complementary metal-oxide semiconductor) semiconductor fabrication which includes providing at least two wells including dopants. A pad layer may be formed on a top surface of the substrate and a partial STI trench is etched in the upper portion of the substrate followed by etching to form a full STI trench. Boron is implanted in a lower area of the full STI trench forming an implant area which is anodized to form a porous silicon region, which is then oxidized to form a oxidized region. A dielectric layer is formed over the silicon nitride layer filling the full STI trench to provide, after etching, at least two electrical component areas on the top surface of the substrate having the full STI trench therebetween.

摘要翻译： 公开了一种用于在CMOS（互补金属氧化物半导体）半导体制造期间在衬底中形成STI（浅沟槽隔离）的方法，其包括提供至少两个包括掺杂剂的阱。 衬底层可以形成在衬底的顶表面上，并且在衬底的上部蚀刻部分STI沟槽，然后蚀刻以形成完整的STI沟槽。 硼被植入整个STI沟槽的下部区域，形成一个阳极氧化以形成多孔硅区域的植入区域，然后被氧化形成氧化区域。 在填充整个STI沟槽的氮化硅层上形成介电层，在蚀刻之后，在衬底的顶表面上提供至少两个具有全部STI沟槽的电气部件区域。

公开(公告)号：US07569489B2

公开(公告)日：2009-08-04

申请号：US11851464

申请日：2007-09-07

申请人： Thomas W. Dyer ,  Haining S. Yang

发明人： Thomas W. Dyer ,  Haining S. Yang

IPC分类号： H01L21/302

CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/04 ,  H01L29/66795 ,  H01L29/7853

摘要： The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.

摘要翻译： 本发明涉及高性能三维（3D）场效应晶体管（FET）。 具体而言，可以使用具有沿着第一组等效晶面中的一个取向的底表面和沿着第二不同组的等效晶面取向的多个附加表面的3D半导体结构，以形成具有载体通道定向的高性能3D FET 沿着第二个不同组的等效晶面。 更重要的是，这种3D半导体结构可以容易地在具有底表面和多个附加表面的附加3D半导体结构的同一衬底上形成，所述另外的三维半导体结构全部沿着第一组等效晶面取向。 附加的3D半导体结构可以用于形成附加的3D FET，其与上述3D FET互补，并且具有沿着第一组等效晶面取向的载流子通道。

公开(公告)号：US07566949B2

公开(公告)日：2009-07-28

申请号：US11380692

申请日：2006-04-28

申请人： Thomas W. Dyer ,  Haining S. Yang

发明人： Thomas W. Dyer ,  Haining S. Yang

IPC分类号： H01L29/04

CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/04 ,  H01L29/66795 ,  H01L29/7853

摘要： The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.

公开(公告)号：US20080283962A1

公开(公告)日：2008-11-20

申请号：US11748521

申请日：2007-05-15

申请人： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

发明人： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

IPC分类号： H01L29/00 ,  H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/3086 ,  H01L21/823878

摘要： A pedestal is formed out of the pad layer such that two edges of the pedestal coincide with a border of the wells as implanted. An extended pedestal is formed over the pedestal by depositing a conformal dielectric layer. The area of the extended pedestal is exposed the semiconductor surface below is recessed to a recess depth. Other trenches including at least one intra-well isolation trench are lithographically patterned. After a reactive ion etch, both an inter-well isolation trench and at least one intra-well isolation trench are formed. The width of the inter-well isolation trench may be reduced due to the deeper bottom surface compared to the prior art structures. The boundary between the p-well and the n-well below the inter-well isolation structure is self-aligned to the middle of the inter-well isolation structure.

摘要翻译： 从衬垫层形成基座，使得底座的两个边缘与植入的孔的边界重合。 通过沉积保形介电层在基座上形成延伸基座。 扩展基座的面积暴露在下方的半导体表面凹陷到凹陷深度。 包括至少一个井内隔离沟槽的其它沟槽被光刻图案化。 在反应离子蚀刻之后，形成阱间隔离沟槽和至少一个阱间隔离沟槽。 与现有技术的结构相比，由于较深的底面，间隙隔离沟槽的宽度可能会降低。 在井间隔离结构下面的p阱和n阱之间的边界与井间隔离结构的中间自对准。

公开(公告)号：US07452758B2

公开(公告)日：2008-11-18

申请号：US11686013

申请日：2007-03-14

申请人： Thomas W. Dyer ,  Haining S. Yang

发明人： Thomas W. Dyer ,  Haining S. Yang

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： There is a FinFET device. The device has a silicon substrate, an oxide layer, and a polysilicone gate. The silicon substrate defines a planar body, a medial body, and a fin. The planar body, the medial body, and the fin are integrally connected. The medial body connects the planar body and the fin. The planar body extends generally around the medial body. The fin is situated to extend substantially from a first side of the substrate to an opposing second side of the substrate. The fin is substantially perpendicularly disposed with respect to the planar body. The first oxide layer is situated on the planar body between the planar body and the fin. The oxide layer extends substantially around the medial body. The polysilicone gate is situated on the oxide layer to extend substantially from a third side to an opposing fourth side of the substrate. The gate is situated to extend across the fin proximal to a medial portion of an upper surface of the fin. There is also a process for making a FinFET device.

摘要翻译： 有一个FinFET器件。 该器件具有硅衬底，氧化物层和多晶硅栅极。 硅衬底限定平面体，中间体和翅片。 平面体，内侧体和翅片整体连接。 内侧主体连接平面体和翅片。 平面体通常围绕内侧身体延伸。 翅片位于基本上从基板的第一侧延伸到基板的相对的第二侧。 翅片相对于平面主体基本垂直设置。 第一氧化物层位于平面体和翅片之间的平面体上。 氧化物层基本上围绕内侧本体延伸。 多晶硅栅极位于氧化物层上，基本上从衬底的第三侧延伸到相对的第四侧。 闸门位于靠近翅片上表面的中间部分延伸穿过翅片。 还有一种制造FinFET器件的过程。

公开(公告)号：US20080237749A1

公开(公告)日：2008-10-02

申请号：US11692402

申请日：2007-03-28

申请人： Huilong Zhu ,  Thomas W. Dyer ,  Haining S. Yang

发明人： Huilong Zhu ,  Thomas W. Dyer ,  Haining S. Yang

IPC分类号： H01L29/76

CPC分类号： H01L21/28044 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/78

摘要： A gate conductor is provided for a transistor pair including an n-type field effect transistor (“NFET”) having an NFET active semiconductor region and a p-type field effect transistor (“PFET”) having a PFET active semiconductor region, where the NFET and PFET active semiconductor regions are separated by an isolation region. An NFET gate extends in a first direction over the NFET active semiconductor region. A PFET gate extends in the first direction over the PFET active semiconductor region. A diffusion barrier is sandwiched between the NFET gate and the PFET gate. A continuous layer extends continuously in the first direction over the NFET gate and the PFET gate. The continuous layer contacts top surfaces of the NFET gate and the PFET gate and the continuous layer includes at least one of a semiconductor, a metal or a conductive compound including a metal.

摘要翻译： 为包括具有NFET有源半导体区域的n型场效应晶体管（“NFET”）和具有PFET有源半导体区域的p型场效应晶体管（“PFET”）的晶体管对，提供栅极导体，其中 NFET和PFET有源半导体区域被隔离区隔开。 NFET栅极在NFET有源半导体区域上的第一方向上延伸。 PFET栅极在PFET有源半导体区域上沿第一方向延伸。 扩散势垒夹在NFET栅极和PFET栅极之间。 连续层在NFET栅极和PFET栅极上在第一方向上连续延伸。 连续层接触NFET栅极和PFET栅极的顶表面，并且连续层包括半导体，金属或包括金属的导电化合物中的至少一种。

公开(公告)号：US20080179678A1

公开(公告)日：2008-07-31

申请号：US11627653

申请日：2007-01-26

申请人： Thomas W. Dyer ,  Haining S. Yang

发明人： Thomas W. Dyer ,  Haining S. Yang

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L21/8238

CPC分类号： H01L27/0694 ,  H01L21/84 ,  H01L27/1203

摘要： Both sides of a semiconductor-on-insulator substrate are utilized to form MOSFET structures. After forming first type devices on a first semiconductor layer, a handle wafer is bonded to the top of a first middle-of-line dielectric layer. A lower portion of a carrier substrate is then removed to expose a second semiconductor layer and to form second type devices thereupon. Conductive vias may be formed through the buried insulator layer to electrically connect the first type devices and the second type devices. Use of block masks is minimized since each side of the buried insulator has only one type of devices. Two levels of devices are present in the structure and boundary areas between different types of devices are reduced or eliminated, thereby increasing packing density of devices. The same alignment marks may be used to align the wafer either front side up or back side up.

摘要翻译： 利用绝缘体上半导体衬底的两侧形成MOSFET结构。 在第一半导体层上形成第一类型器件之后，把手晶片结合到第一中间线介电层的顶部。 然后移除载体衬底的下部以暴露第二半导体层并在其上形成第二类型器件。 可以通过掩埋绝缘体层形成导电孔，以电连接第一类型器件和第二类型器件。 掩模掩模的使用最小化，因为埋入绝缘体的每一侧只有一种类型的器件。 结构中存在两级装置，减少或消除不同类型装置之间的边界区域，从而提高装置的包装密度。 可以使用相同的对准标记来将晶片的前侧向上或向后对准。