公开(公告)号：US20220300374A1

公开(公告)日：2022-09-22

申请号：US17648395

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Jonathan S. Parry ,  Deping He ,  Xiangang Luo ,  Reshmi Basu

IPC: G06F11/10

Abstract: Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.

公开(公告)号：US20220291849A1

公开(公告)日：2022-09-15

申请号：US17751026

申请日：2022-05-23

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Karl D. Schuh ,  Jiangang Wu ,  Mastafa N. Kaynak ,  Devin M. Batutis ,  Xiangang Luo

IPC: G06F3/06

Abstract: Method includes identifying, while programming sets of pages to dice of memory device, multiple sets of pages experiencing a variation in temporal voltage shift satisfying a threshold criterion; partitioning a set of pages of the multiple sets of pages into a set of fixed-length partitions; storing, in a metadata table, a value to indicate a size of each fixed-length partition; receiving a read operation directed at a page of the set of pages; determining, based on a logical block address of the read operation and on the value that indicates the size of each fixed-length partition, a partition of the set of fixed-length partitions to which the read operation corresponds; and searching within the metadata table to determine a block family to which the partition is assigned, wherein the searching is based on a first value associated with the set of pages and a second value associated with the partition.

公开(公告)号：US20220261313A1

公开(公告)日：2022-08-18

申请号：US17734444

申请日：2022-05-02

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Lakshmi Kalpana Vakati ,  Harish R. Singidi

IPC: G06F11/10 ,  G06F3/06

Abstract: A parity generation operation based on a set of multiple planes of host data is executed to generate a set of multi-page parity data. The set of multi-page parity data is stored in a cache memory of a memory device. A data recovery operation is performed based on the set of multi-page parity data.

公开(公告)号：US20220084605A1

公开(公告)日：2022-03-17

申请号：US16948359

申请日：2020-09-15

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Shane Nowell ,  Mustafa N. Kaynak ,  Karl D. Schuh ,  Jiangang Wu ,  Devin M. Batutis ,  Xiangang Luo

IPC: G11C16/34 ,  G06F3/06 ,  G06F11/07 ,  G11C16/26

Abstract: A system includes a memory device and a processing device. The processing device performs, at a first frequency, a first scan of a page of a block family that measures a first data state metric and identifies a specific bin corresponding to a measured value for the first data state metric. Processing device updates a bin, to which the page is assigned, to match the specific bin. Processing device performs, at a second frequency higher than the first frequency, a second scan of the page to measure a second data state metric for read operations performed using a threshold voltage offset value from each of multiple bins. Processing device updates the bin, to which the page is assigned for the specified die, to match a second bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan.

公开(公告)号：US20220083463A1

公开(公告)日：2022-03-17

申请号：US16948302

申请日：2020-09-11

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Karl D. Schuh ,  Jiangang Wu ,  Mustafa N. Kaynak ,  Devin M. Batutis ,  Xiangang Luo

IPC: G06F12/02 ,  G06F12/0846 ,  G06F12/0882 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

Abstract: A system includes a memory device having multiple dice and a processing device operatively coupled to the memory device. The processing device is to perform operations, including receiving a memory operation to program a set of pages of data across at least a subset of the plurality of dice. The operations further include partitioning the set of pages into a set of partitions, programming the set of partitions to the plurality of dice, and storing, in a metadata table, at least one bit to indicate that the set of pages is partitioned.

公开(公告)号：US20210390014A1

公开(公告)日：2021-12-16

申请号：US17458224

申请日：2021-08-26

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Falgun G. Trivedi ,  Harish Reddy Singidi ,  Xiangang Luo ,  Preston Allen Thomson ,  Ting Luo ,  Jianmin Huang

IPC: G06F11/10 ,  G06F12/0882 ,  G06F11/07 ,  G06F12/02

Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20210149564A1

公开(公告)日：2021-05-20

申请号：US16685300

申请日：2019-11-15

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Ankit Vinod Vashi ,  Xiangang Luo ,  Jianmin Huang

IPC: G06F3/06

Abstract: Techniques disclosed herein can be used to improve cross-temperature coverage of memory devices and improve memory device reliability in cross-temperature conditions. More specifically, a memory trim set can be selected from multiple candidate memory trim sets when performing a memory operation (such as a memory write operation), based on a temperature metric and a P/E cycle metric for the memory device. The candidate memory trim sets include multiple respective memory trim values (e.g., memory configuration parameters, such as program voltage step size, program pulse width, program verify level, etc., as discussed above) for performing the memory operation. The temperature metric can be indicative of a temperature of at least a region of the memory device (e.g., the entire device, a memory plane, a memory block, etc.), and the P/E cycle metric can be indicative of a number of P/E cycles performed by the memory device within a selected time interval.

公开(公告)号：US20210064495A1

公开(公告)日：2021-03-04

申请号：US16560560

申请日：2019-09-04

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Xiangang Luo ,  Kulachet Tanpairoj

IPC: G06F11/30 ,  G06F11/07 ,  G06F12/14 ,  G11C16/14 ,  G11C29/02

Abstract: A memory device comprises a memory control unit including a processor configured to control operation of the memory array according to a first memory management protocol for memory access operations, the first memory management protocol including boundary conditions for multiple operating conditions comprising program/erase (P/E) cycles, error management operations, drive writes per day (DWPD), and power consumption; monitor operating conditions of the memory array for the PIE cycles, error management operations, DWPD, and power consumption; determine when a boundary condition for one of the multiple operating conditions is met; and in response to determining that a first boundary condition for a first monitored operating condition is met, change one or more operating conditions of the first memory management protocol to establish a second memory management protocol for the memory access operations, the second memory management protocol including a change boundary condition of a second monitored operating condition.

公开(公告)号：US20200210280A1

公开(公告)日：2020-07-02

申请号：US16267586

申请日：2019-02-05

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Xiangang Luo ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC: G06F11/10 ,  G06F11/14

Abstract: A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.

公开(公告)号：US20250104799A1

公开(公告)日：2025-03-27

申请号：US18788730

申请日：2024-07-30

Applicant: Micron Technology, Inc.

Inventor： Guang Hu ,  Xiangang Luo ,  Jianmin Huang

IPC: G11C29/00

Abstract: Aspects of the present disclosure configure a memory sub-system controller to generate virtual blocks using partial good blocks or portions of full blocks. The controller identifies a region of a set of memory components comprising a plurality of planes across a plurality of decks. The controller determines that a first memory block within a first deck associated with a first plane of the plurality of planes is a first partial good block (PGB), the first PGB including a portions categorized as being defective and portions categorized as being non-defective. The controller determines that a second memory block associated with a second plane is a full block (FB), the FB being categorized as non-defective. The controller generates a virtual block using the first PGB of the first memory block associated with the first plane and a portion of the FB of the second memory block associated with the second plane.