公开(公告)号：US20210120099A1

公开(公告)日：2021-04-22

申请号：US17135774

申请日：2020-12-28

Applicant: Micron Technology, Inc.

Inventor： Parag R. Maharana ,  Anirban Ray ,  Gurpreet Anand

IPC: H04L29/08 ,  G06F9/455 ,  G06F12/02

Abstract: A memory system having one or more memory components and a controller. The controller can receive access requests from a communication connection. The access requests can identify data items associated with the access requests, addresses of the data items, and contexts of the data items in which the data items are used for the access requests. The controller can identify separate memory regions for separate contexts respectively, determine placements of the data items in the separate memory regions based on the contexts of the data items, and determine a mapping between the addresses of the data items and memory locations that are within the separate memory regions corresponding to the contexts of the data items. The memory system stores store the data items at the memory locations separated by different memory regions according to different contexts.

公开(公告)号：US10691611B2

公开(公告)日：2020-06-23

申请号：US16035469

申请日：2018-07-13

Applicant: Micron Technology, Inc.

Inventor： Anirban Ray ,  Parag R. Maharana

IPC: G06F12/1009 ,  G06F12/02 ,  G06F9/50 ,  G06F9/455 ,  G06F9/30

Abstract: A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: store a memory ratio in association with a context of executing instructions; execute a set of instructions in the context; allocate, for execution of the set of instructions in the context, an amount of memory, including an amount of the first memory and an amount of the second memory; and access the amount of the second memory via the amount of the first memory during the execution of the set of instructions in the context. A ratio between the amount of the first memory and an amount of the second memory allocated for the execution of the set of instructions in the context is in accordance with the memory ratio.

公开(公告)号：US20200042246A1

公开(公告)日：2020-02-06

申请号：US16355271

申请日：2019-03-15

Applicant: Micron Technology, Inc.

Inventor： Parag R. Maharana ,  Anirban Ray ,  Gurpreet Anand ,  Samir Rajadnya ,  Paul Stonelake ,  Samir Mittal

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42

Abstract: A system controller, operatively coupled with one or more memory devices, is configured to provide a plurality of virtual memory controllers, wherein each of the plurality of virtual memory controllers is associated with a different portion of the one or more memory devices, and provide a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers. The system controller further presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface, the host computing system to assign each of the plurality of physical functions to a different virtual machine running on the host computing system.

公开(公告)号：US20200019506A1

公开(公告)日：2020-01-16

申请号：US16032331

申请日：2018-07-11

Applicant: Micron Technology, Inc.

Inventor： Anirban Ray ,  Samir Mittal ,  Gurpreet Anand ,  Parag R. Maharana

IPC: G06F12/0862 ,  G06F12/1009 ,  G06F12/0871 ,  G06F12/0873 ,  G06F9/455 ,  G06N3/08

Abstract: A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, in a prediction engine, usage history of pages in the second memory; train a prediction model based on the usage history; predict, by the prediction engine using the prediction model, likelihood of the pages being used in a subsequent period of time; and responsive to the likelihood predicted by the prediction engine, copy by a controller data in a page in the second memory to the first memory.

公开(公告)号：US20190243756A1

公开(公告)日：2019-08-08

申请号：US16054719

申请日：2018-08-03

Applicant: Micron Technology, Inc.

Inventor： Anirban Ray ,  Parag R. Maharana ,  Gurpreet Anand

IPC: G06F12/0802 ,  G06F12/02 ,  G06F9/50

CPC classification number: G06F12/0802 ,  G06F9/5077 ,  G06F12/0238 ,  G06F16/972

Abstract: A computing system having at least one bus, a plurality of different memory components, and a processing device operatively coupled with the plurality of memory components through the at least one bus. The different memory components include first memory and second memory having different memory access speeds. The computing system further includes a memory virtualizer operatively to: store an address map between first addresses used by the processing device to access memory and second addresses used to access the first memory and the second memory; monitor usages of the first memory and the second memory; adjust the address map based on the usages to improve speed of the processing device in memory access involving the first memory and the second memory; and swap data content in the first memory and the second memory according to adjustments to the address map.

公开(公告)号：US20190243570A1

公开(公告)日：2019-08-08

申请号：US16054819

申请日：2018-08-03

Applicant: Micron Technology, Inc.

Inventor： Samir Mittal ,  Anirban Ray ,  Gurpreet Anand

IPC: G06F3/06 ,  G06F12/0811 ,  G06F13/16 ,  G06N3/08

Abstract: A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.

公开(公告)号：US11977787B2

公开(公告)日：2024-05-07

申请号：US17382200

申请日：2021-07-21

Applicant: Micron Technology, Inc.

Inventor： Parag R. Maharana ,  Anirban Ray ,  Gurpreet Anand ,  Samir Mittal

IPC: G06F3/06 ,  G06F12/00 ,  G06F13/28 ,  G06F15/173 ,  G11C14/00 ,  H04L67/1097

CPC classification number: G06F3/067 ,  G06F12/00 ,  G06F13/28 ,  G06F15/17331 ,  G11C14/0009 ,  H04L67/1097

Abstract: A memory system having memory components, a remote direct memory access (RDMA) network interface card (RNIC), and a host system, and configured to: allocate a page of virtual memory for an application; map the page of virtual memory to a page of physical memory in the memory components; instruct the RNIC to perform an RDMA operation; perform, during the RDMA operation, a data transfer between the page of physical memory in the plurality of memory components and a remote device that is connected via a computer network to the remote direct memory access network interface card; and at least for a duration of the data transfer, lock a mapping between the page of virtual memory and the page of physical memory in the memory components.

公开(公告)号：US11561902B2

公开(公告)日：2023-01-24

申请号：US17450124

申请日：2021-10-06

Applicant: Micron Technology, Inc.

Inventor： Paul Stonelake ,  Horia C. Simionescu ,  Samir Mittal ,  Robert W. Walker ,  Anirban Ray ,  Gurpreet Anand

IPC: G06F12/0811 ,  G06F12/0897 ,  G06F12/0888 ,  G06F12/0862

Abstract: A system includes a first memory device of a first memory type, a second memory device of a second memory type, and a third memory device of a third memory type. The system further includes a processing device to retrieve one or more sections of data from the first memory device comprising a first memory type, and retrieve one or more remaining sections of data from the second memory device comprising a second memory type, wherein the one or more remaining sections of data from the second memory device are associated with the one or more sections of data from the first memory device. The processing device is further to combine the one or more sections of data from the first memory device comprising the first memory type with the one or more remaining sections of each of data from the second memory device comprising the second memory type into a contiguous page, and copy the contiguous page to a third memory device comprising a third memory type.

公开(公告)号：US20220326868A1

公开(公告)日：2022-10-13

申请号：US17729738

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Samir Mittal ,  Anirban Ray ,  Gurpreet Anand

IPC: G06F3/06 ,  G06F12/0811 ,  G06F13/16 ,  G06N3/08

Abstract: A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.

公开(公告)号：US20210405913A1

公开(公告)日：2021-12-30

申请号：US17304450

申请日：2021-06-21

Applicant: Micron Technology, Inc.

Inventor： Paul Stonelake ,  Anirban Ray ,  David Boles

IPC: G06F3/06

Abstract: A processing device in a memory system tracks a plurality of memory access operations directed to a plurality of segments of data on the memory device and maintains a plurality of access counters corresponding to the plurality of segments. The processing device sorts the plurality of segments based on values of the corresponding access counters and filters the plurality of segments to identify a subset of the plurality of segments for which the values of the corresponding access counters satisfy a threshold criterion. The processing device further generates a notification comprising an indication of the subset of the plurality of segments and provides the notification to a host system after the expiration of a periodic interval.