公开(公告)号：US20230027926A1

公开(公告)日：2023-01-26

申请号：US17381860

申请日：2021-07-21

Applicant: Micron Technology, Inc.

Inventor： Shindeok Kang ,  Timothy M. Hollis ,  Dragos Dimitriu

IPC: G11C11/56 ,  G11C7/02

Abstract: Methods, systems, and devices related to an improved driver for non-binary signaling are described. A driver for a signal line may include a set of drivers of a first type and a set of drivers of a second type. When the driver drives the signal line using multiple drivers of the first type, at least one additional driver of the first type may compensate for non-linearities associated with one or more other drivers of the first type, which may have been calibrated at other voltages. The at least one additional driver of the first type may be calibrated for use at a particular voltage, to compensate for non-linearities associated with the one or more other drivers of the first type as exhibited at that particular voltage.

公开(公告)号：US10861531B2

公开(公告)日：2020-12-08

申请号：US16375770

申请日：2019-04-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Dragos Dimitriu

IPC: G11C7/22 ,  G11C11/4074 ,  G11C7/10 ,  G11C8/06 ,  G11C11/4096 ,  G11C11/4093 ,  G11C5/06 ,  G11C11/4076

Abstract: Apparatuses and methods for providing additional drive to multilevel signals representing data are described. An example apparatus includes a first driver section, a second driver section, and a third driver section. The first driver section is configured to drive an output terminal toward a first selected one of a first voltage and a second voltage. The second driver section configured to drive the output terminal toward a second selected one of the first voltage and the second voltage. The third driver section configured to drive the output terminal toward the first voltage when each of the first selected one and the second selected one is the first voltage. The third driver circuit is further configured to be in a high impedance state when the first selected one and the second selected one are different from each other.

公开(公告)号：US20190109057A1

公开(公告)日：2019-04-11

申请号：US16029199

申请日：2018-07-06

Applicant: Micron Technology, Inc.

Inventor： Ebrahim H. Hargan ,  Layne Bunker ,  Dragos Dimitriu ,  Gregory A. King

IPC: H01L21/66 ,  H01L25/065 ,  G01R31/28

Abstract: A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.

公开(公告)号：US20190036743A1

公开(公告)日：2019-01-31

申请号：US16128017

申请日：2018-09-11

Applicant: Micron Technology, Inc.

Inventor： Dragos Dimitriu

IPC: H04L25/03 ,  H04L7/00

CPC classification number: H04L25/03057 ,  G11C7/222 ,  H04L7/0079 ,  H04L25/03146

Abstract: Various embodiments include apparatus and methods having a data receiver with a real time clock decoding decision feedback equalizer. In various embodiments, a digital decision feedback loop can be implemented in a data receiver circuit, while all analog signals involved are static relative to the input signal data rate. The implemented data receiver circuit can include a number of data latches with different, but static, analog unbalances and a decision-based clock decoder. In an example, the analog unbalances may be different reference voltages. The decision-based clock decoder can be structured to activate only one data latch, the one with the desired analog unbalance. The outputs of the latches attached to the same clock decoder can be combined such that only the active latch drives the final output. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20140049244A1

公开(公告)日：2014-02-20

申请号：US14059095

申请日：2013-10-21

Applicant: Micron Technology, Inc.

Inventor： Dragos Dimitriu ,  Timothy Hollis

IPC: G05F3/08

CPC classification number: G05F3/08 ,  H03K19/0175

Abstract: An improved reference voltage (Vref) generator useable, for example, in sensing data on single-ended channels is disclosed. The Vref generator can be placed on the integrated circuit containing the receivers, or may be placed off chip. In one embodiment, the Vref generator comprises an adjustable-resistance voltage divider in combination with a current source. The voltage divider is referenced to I/O power supplies Vddq and Vssq, with Vref being generated at a node intervening between the adjustable resistances of the voltage divider. The current source injects a current into the Vref node and into a non-varying Thevenin equivalent resistance formed of the same resistors used in the voltage divider. So constructed, the voltage generated equals the sum of two terms: a first term comprising the slope between Vref and Vddq, and a second term comprising a Vref offset. Each of these terms can be independently adjusted in first and second modes: the slope term via the voltage divider, and the offset term by the magnitude of the injected current. Use of the disclosed Vref generator in one useful implementation allows Vref to be optimized at two different values for Vddq.

Abstract translation: 公开了一种改进的参考电压（Vref）发生器，可用于例如感​​测单端通道上的数据。 Vref发生器可以放置在包含接收器的集成电路上，或者可以放在芯片外。 在一个实施例中，Vref发生器包括与电流源组合的可调电阻分压器。 分压器参考I / O电源Vddq和Vssq，其中Vref在分压器的可调电阻之间的节点处产生。 电流源将电流注入到Vref节点中，并将其分成由分压器中使用的相同电阻器形成的不变的戴维南等效电阻。 所产生的电压等于两个项的和：包括Vref和Vddq之间的斜率的第一项，以及包括Vref偏移的第二项。 这些术语中的每一个可以在第一和第二模式中独立调整：通过分压器的斜率项，以及偏移项由注入电流的大小。 在一个有用的实现中使用所公开的Vref发生器允许在Vddq的两个不同值处优化Vref。