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公开(公告)号：US20140115299A1
公开(公告)日：2014-04-24
申请号：US14143398
申请日：2013-12-30
Applicant: Micron Technology, Inc.
Inventor： Harold B Noyes , David R. Brown , Paul Glendenning
IPC: G06F15/82
CPC classification number: G05B19/045 , G06F9/4498 , G06F15/82 , G06F21/567 , G06F2207/025 , G06N5/047 , H03K19/17724 , H03K19/17748
Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers.
Abstract translation: 公开了方法和装置，其中包括有限状态机格的装置。 格子可以包括适合于对格子中的可编程元件检测到条件的次数进行计数的计数器。 计数器可以配置为响应于计数而输出，条件被检测到一定次数。 例如，计数器可以被配置为响应于确定至少（或不超过）一定次数检测到的条件而输出，确定条件被精确地检测到一定次数，或者确定检测到条件 在一定的时间范围内。 计数器可以耦合到设备中的其他计数器，用于确定高计数操作和/或某些量化器。
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公开(公告)号：US20250139011A1
公开(公告)日：2025-05-01
申请号：US19006769
申请日：2024-12-31
Applicant: Micron Technology, Inc.
Inventor： David R. Brown , Harold B Noyes , Inderjit Singh Bains
IPC: G06F12/0875 , G06F3/06 , G06F9/448 , G06N3/02
Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.
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公开(公告)号：US12216584B2
公开(公告)日：2025-02-04
申请号：US18527793
申请日：2023-12-04
Applicant: Micron Technology, Inc.
Inventor： David R. Brown , Harold B Noyes , Inderjit Singh Bains
IPC: G06F12/08 , G06F3/06 , G06F9/448 , G06F12/0875 , G06N3/02
Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.
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公开(公告)号：US11768798B2
公开(公告)日：2023-09-26
申请号：US17550593
申请日：2021-12-14
Applicant: Micron Technology, inc.
Inventor： Harold B Noyes , David R. Brown
IPC: G06F15/80 , G06F16/903 , H03K19/17728 , G06V10/94 , G06V10/70 , G06N5/01
CPC classification number: G06F15/80 , G06F16/90344 , G06N5/01 , G06V10/768 , G06V10/955 , H03K19/17728
Abstract: Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.
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公开(公告)号：US11599770B2
公开(公告)日：2023-03-07
申请号：US16715755
申请日：2019-12-16
Applicant: Micron Technology, Inc.
Inventor： Harold B Noyes , David R. Brown
IPC: G06F9/448 , G06F15/78 , G06N3/04 , G05B19/045 , G06N3/02
Abstract: A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state machine lattice. The state machine engine also includes a repair map buffer configured to provide repair map data to an external device via the bus interface. The state machine lattice includes multiple programmable elements. Each programmable element includes multiple memory cells configured to analyze data and to output a result of the analysis.
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Patent Agency Ranking
公开(公告)号：US20220261257A1
公开(公告)日：2022-08-18
申请号：US17736399
申请日：2022-05-04
Applicant: Micron Technology Inc.
Inventor： Harold B Noyes , David R. Brown , Paul Giendenning
Abstract: A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.
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公开(公告)号：US11366675B2
公开(公告)日：2022-06-21
申请号：US16525187
申请日：2019-07-29
Applicant: Micron Technology, inc.
Inventor： Harold B Noyes , David R. Brown , Paul Glendenning
Abstract: A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.
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28.发明申请公开(公告)号：US20190354530A1
公开(公告)日：2019-11-21
申请号：US16527217
申请日：2019-07-31
Applicant: Micron Technology, inc.
Inventor： Harold B Noyes
IPC: G06F16/2455 , G06F13/28 , G06F13/42
Abstract: Disclosed are methods and devices, among which is a system that includes a device that includes one or more pattern-recognition processors in a pattern-recognition cluster, for example. One of the one or more pattern-recognition processors may be initialized to perform as a direct memory access master device able to control the remaining pattern-recognition processors for synchronized processing of a data stream.
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公开(公告)号：US20190354380A1
公开(公告)日：2019-11-21
申请号：US16525187
申请日：2019-07-29
Applicant: Micron Technology, Inc.
Inventor： Harold B Noyes , David R. Brown , Paul Glendenning
Abstract: A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.
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公开(公告)号：US20190340130A1
公开(公告)日：2019-11-07
申请号：US16513418
申请日：2019-07-16
Applicant: Micron Technology, Inc.
Inventor： David R. Brown , Harold B Noyes , Inderjit Singh Bains
IPC: G06F12/0875 , G06F3/06 , G06N3/02 , G06F9/448
Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.
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