公开(公告)号：US11619964B2

公开(公告)日：2023-04-04

申请号：US17385412

申请日：2021-07-26

Applicant: Micron Technology, Inc.

Inventor： Hyunui Lee ,  Won Joo Yun

IPC: G06F1/12 ,  G06F1/10 ,  G06F1/08

Abstract: Methods for improving timing in memory devices are disclosed. A method may include sampling a command signal according to a clock signal to obtain standard-timing commands. The method may also include sampling the command signal according to an adjusted clock signal to obtain time-adjusted commands. The method may also include comparing the standard-timing commands and the time-adjusted commands. The method may also include determining an improved timing for the clock signal based on the comparison of the standard-timing commands and the time-adjusted commands. The method may also include adjusting the clock signal based on the improved timing. Associated systems and methods are also disclosed.

公开(公告)号：US20230062002A1

公开(公告)日：2023-03-02

申请号：US18048588

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Hyunui Lee

IPC: G06F9/445 ,  G11C11/4093 ,  G11C7/10 ,  G06F3/06 ,  G06F13/20

Abstract: A device may include a number of drivers, wherein each driver of the number of drivers includes a number of transistors coupled to an output node. The device may further include circuitry coupled to the number of drivers. The circuitry may configure at least one driver of the number of drivers in each of a number of configurations, wherein each configuration of the number of configurations is associated with a calibration code of a number of calibration codes. Each configuration generates, in response to signal transmission via the output node, an associated channel performance response of a number of channel performance responses. The circuitry may also store a calibration code for the at least one unit driver, wherein the calibration code generates a desired channel performance response of the number of channel performance responses. Systems and related methods of operation are also described.

公开(公告)号：US20220246193A1

公开(公告)日：2022-08-04

申请号：US17720048

申请日：2022-04-13

Applicant: Micron Technology, Inc.

Inventor： Hyunui Lee ,  Takamasa Suzuki ,  Yasuo Satoh ,  Yuan He

IPC: G11C11/4074 ,  G11C11/4091 ,  G11C11/4063 ,  G11C11/4099 ,  H01L27/108

Abstract: Some embodiments include an integrated assembly having a deck over a base, and having memory cells supported by the deck. Each of the memory cells includes a capacitive unit and a transistor. The individual capacitive units of the memory cells each have a storage node electrode, a plate electrode, and a capacitor dielectric material between the storage node electrode and the plate electrode. A reference-voltage-generator includes resistive units supported by the deck. The resistive units are similar to the memory cells but include interconnecting units in place of the capacitive units. The interconnecting units of some adjacent resistive units are shorted to one another.

公开(公告)号：US20210391028A1

公开(公告)日：2021-12-16

申请号：US17446559

申请日：2021-08-31

Applicant: Micron Technology, Inc.

Inventor： Hyunui Lee

IPC: G11C29/12 ,  G11C7/10 ,  G11C29/02

Abstract: Semiconductor devices are disclosed. A semiconductor device may include a number of impedance calibration circuits and an interpolation circuit. The interpolation circuit may be configured to generate a calibration code based on two or more other calibration codes generated via one or more impedance calibration circuits of the number of impedance calibration circuits, another interpolation circuit, or any combination thereof. Methods and systems are also disclosed.

公开(公告)号：US10790039B1

公开(公告)日：2020-09-29

申请号：US16584520

申请日：2019-09-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyunui Lee ,  Chiaki Dono

IPC: G11C29/02 ,  G11C29/12 ,  G11C29/48 ,  H01L23/48 ,  H01L23/498 ,  H01L27/108 ,  G11C29/30 ,  G11C29/56 ,  G11C29/44

Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip including a data I/O terminal, a test terminal, a first data input node, a first data output node, a read circuit, a write circuit, and a test circuit configured to transfer a test data supplied from the test terminal to the read circuit, and a second semiconductor chip including a second data input node connected to the first data output node, a second data output node connected to the first data input node, and a memory cell array. The test circuit is configured to activate the read circuit, the write circuit and the memory cell array so that the test data is written into the memory cell array via the read circuit, the data I/O terminal, the write circuit, the first data output node, and the second data input node.