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公开(公告)号：US11139016B1
公开(公告)日：2021-10-05
申请号：US16842524
申请日：2020-04-07
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Karthik Sarpatwari , Innocenzo Tortorelli , Nevil N. Gajera
IPC: G11C7/00 , G11C11/406 , G11C11/409 , G11C11/4076 , G11C11/4074
Abstract: Methods, systems, and devices for read refresh operations are described. A memory device may include a plurality of sub-blocks of memory cells. Each sub-block may undergo a quantity of access operations (e.g., read operations, write operations). Based on the quantity of access operations performed on any one sub-block over a period of time, a read refresh operation may be performed on the memory cells of the sub-block. A read refresh operation may refresh and/or restore the data stored to the memory cells of the sub-block, and be initiated based on the memory device receiving an operation code (e.g., from a host device).
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公开(公告)号：US11114613B2
公开(公告)日：2021-09-07
申请号：US16866302
申请日：2020-05-04
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Innocenzo Tortorelli , Andrea Ghetti
Abstract: The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.
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公开(公告)号：US11114159B2
公开(公告)日：2021-09-07
申请号：US16876641
申请日：2020-05-18
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Mattia Robustelli , Innocenzo Tortorelli , Mario Allegra , Paolo Amato
Abstract: In an example, a first data structure can be read with a first read voltage dedicated to the first data structure. A second data structure that stores a larger quantity of data than the first data structure can be with a second read voltage that is dedicated to the second data structure. The first data structure can be with a third read voltage in response to a quantity of errors in reading the first data structure being greater than or equal to a first threshold quantity. The second data structure can be read with the third read voltage in response to a quantity of errors in reading the second data structure being greater than or equal to a second threshold quantity. The read voltages can be based on a temperature of an apparatus that includes the first and second data structures.
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公开(公告)号：US10976936B2
公开(公告)日：2021-04-13
申请号：US15683821
申请日：2017-08-23
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Innocenzo Tortorelli
Abstract: The present disclosure includes apparatuses and methods related to sensing operations in memory. An example apparatus can perform sensing operations on an array of memory cells by applying a first signal to a first portion of the array of memory cells and a second signal to a second portion of the array of memory cells.
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公开(公告)号：US20210043838A1
公开(公告)日：2021-02-11
申请号：US17069380
申请日：2020-10-13
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Mattia Robustelli
Abstract: Methods and devices based on the use of dopant-modulated etching are described. During fabrication, a memory storage element of a memory cell may be non-uniformly doped with a dopant that affects a subsequent etching rate of the memory storage element. After etching, the memory storage element may have an asymmetric geometry or taper profile corresponding to the non-uniform doping concentration. A multi-deck memory device may also be formed using dopant-modulated etching. Memory storage elements on different memory decks may have different taper profiles and different doping gradients.
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Patent Agency Ranking
公开(公告)号：US20200335551A1
公开(公告)日：2020-10-22
申请号：US16385636
申请日：2019-04-16
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli
Abstract: Methods, systems, and devices for multi-component cell architectures for a memory device are described. A memory device may include self-selecting memory cells that include multiple self-selecting memory components (e.g., multiple layers or other segments of a self-selecting memory material, separated by electrodes). The multiple self-selecting memory components may be configured to collectively store one logic state based on the polarity of a programming pulse applied to the memory cell. The multiple memory component layers may be collectively (concurrently) programmed and read. The multiple self-selecting memory components may increase the size of a read window of the memory cell when compared to a memory cell with a single self-selecting memory component. The read window for the memory cell may correspond to the sum of the read windows of each self-selecting memory component.
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公开(公告)号：US20200152262A1
公开(公告)日：2020-05-14
申请号：US16733152
申请日：2020-01-02
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Innocenzo Tortorelli
Abstract: Methods, systems, and devices for mimicking neuro-biological architectures that may be present in a nervous system are described herein. A memory device may include a memory unit configured to store a value. A memory unit may include a first memory cell (e.g., an aggressor memory cell) and a plurality of other memory cells (e.g., victim memory cells). The memory unit may use thermal disturbances of the victim memory cells that may be based on an access operation to store the analog value. Thermal energy output by the aggressor memory cell during an access operation (e.g., a write operation) may cause the state of the victim memory cells to alter based on thermal relationship between the aggressor memory cell and at least some of the victim memory cells. The memory unit may be read by detecting and combining the weights of the victim memory cells during a read operation.
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公开(公告)号：US10600456B2
公开(公告)日：2020-03-24
申请号：US16215693
申请日：2018-12-11
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Innocenzo Tortorelli , Marco Dallabora
Abstract: The present disclosure includes apparatuses and methods related to program operations in memory. An example apparatus can perform a program operation on an array of memory cells by applying a first program signal to a first portion of the array of memory cells that are to remain in a first state in response to the program operation, wherein the first program signal programs memory cells to a second state and then to the first state.
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公开(公告)号：US20200075858A1
公开(公告)日：2020-03-05
申请号：US16665955
申请日：2019-10-28
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Fabio Pellizzer , Anna Maria Conti , Andrea Redaelli , Innocenzo Tortorelli
Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.
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公开(公告)号：US20200051626A1
公开(公告)日：2020-02-13
申请号：US16102493
申请日：2018-08-13
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Agostino Pirovano , Innocenzo Tortorelli
IPC: G11C13/00
Abstract: Methods, systems, and devices for operating memory cell(s) are described. A resistance of a storage element included in a memory cell may be programmed by applying a voltage to the memory cell that causes ion movement within the storage element, where the storage element remains in a single phase and has different resistivity based on a location of the ions within the storage element. In some cases, multiple of such storage elements may be included in a memory cell, where ions within the storage elements respond differently to electric pulses, and a non-binary logic value may be stored in the memory cell by applying a series of voltages or currents to the memory cell.
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