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公开(公告)号：US11048580B2
公开(公告)日：2021-06-29
申请号：US16796848
申请日：2020-02-20
Applicant: Micron Technology, Inc.
Inventor： Samuel E. Bradshaw , Justin Eno , Sean Stephen Eilert , Sai Krishna Mylavarapu
Abstract: Exemplary methods, apparatuses, and systems include a memory controller receiving a user payload to be written to a memory. The memory controller determines a plurality of locations within the memory within which the user payload will be written. After detecting the destination of the user payload, the memory controller detects, within a data structure, the presence of an identifier of a first location within a user data portion of the plurality of locations. The memory controller writes the user payload to the user data portion of the plurality of locations and, in response to detecting the presence of the identifier in the data structure, writes a copy of one or more bits in the user payload written to the first location to a spare data portion of the plurality of locations.
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公开(公告)号：US10761740B1
公开(公告)日：2020-09-01
申请号：US16421353
申请日：2019-05-23
Applicant: Micron Technology, Inc.
Inventor： Samuel E. Bradshaw , Justin Eno
Abstract: A method for performing wear leveling in a memory subsystem. The method includes adding, in response to a wear-leveling event, a migration association map entry to a migration association map to control copying of a first set of managed units from a first memory segment to a second set of managed units of a second memory segment, wherein adding the migration association map entry includes setting an exchange pointer of the migration association map entry to a value that references an unused managed unit in the first memory segment and copying the first set of managed units to the second set of managed units beginning with a managed unit in the first set of managed units following the managed unit referenced by the exchange pointer of the first segment metadata table entry.
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公开(公告)号：US20240233870A9
公开(公告)日：2024-07-11
申请号：US18049506
申请日：2022-10-25
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Justin Eno , Sean S. Eilert , Ameen D. Akel , Kenneth M. Curewitz
Abstract: Associative processing memory (APM) may be used to align reads to a reference sequence. The APM may store shifted permutations and/or other permutations of the reference sequence. A read may be compared to some or all of the permutations of the reference sequence and the APM may provide an output for each comparison. In some examples, the APM may compare the read to many permutations of the reference sequence to the read in parallel. Inferences may be made based on the comparisons between the read and the portions and/or permutations of a reference sequence. Based on the inferences, a candidate alignment location in the reference sequence for a read to be determined.
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公开(公告)号：US12026051B2
公开(公告)日：2024-07-02
申请号：US17861013
申请日：2022-07-08
Applicant: Micron Technology, Inc.
Inventor： Justin Eno , William A. Melton , Sean S. Eilert
CPC classification number: G06F11/1068 , G06F11/073 , G06F11/076 , G06F11/0772 , G06F11/1064 , G06F11/3037
Abstract: Methods, systems, and devices for adaptive parity techniques for a memory device are described. An apparatus, such as a memory device, may use one or more error correction code (ECC) schemes, an error cache, or both to support access operations. The memory device may receive a command from a host device to read or write data. If the error cache includes an entry for the data, the memory device may read or write the data using a first ECC scheme. If the error cache does not include an entry for the data, the memory device may read or write the data without using an ECC scheme or using a second ECC scheme different than the first ECC scheme.
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公开(公告)号：US12001708B2
公开(公告)日：2024-06-04
申请号：US17647944
申请日：2022-01-13
Applicant: Micron Technology, Inc.
Inventor： Sean S. Eilert , Ameen D. Akel , Justin Eno , Brian Hirano
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: Methods, systems, and devices for in-memory associative processing for vectors are described. A device may perform a computational operation on a first set of contiguous bits of a first vector and a first set of contiguous bits of a second vector. The first sets of contiguous bits may be stored in a first plane of a memory die and the computational operation may be based on a truth table for the computational operation. The device may perform a second computational operation on a second set of contiguous bits of the first vector and a second set of contiguous bits of the second vector. The second sets of contiguous bits may be stored in a second plane of the memory die and the computational operation based on the truth table for the computational operation.
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Patent Agency Ranking
公开(公告)号：US20230009642A1
公开(公告)日：2023-01-12
申请号：US17369869
申请日：2021-07-07
Applicant: Micron Technology, Inc.
Inventor： Sean S. Eilert , Justin Eno , Ameen D. Akel
Abstract: Methods, systems, and devices for programmable metadata and related operations are described. A method may include receiving signaling that indicates a set of rules for transitions of states of metadata at a memory device storing the metadata. The memory device may receive a command from a host device associated with a set of data after receiving the set of rules. The memory device may transition metadata associated with the set of data stored at the memory device from a first state to a second state based in part on the set of rules and the command. The memory device may execute the command received from the host device.
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公开(公告)号：US11385961B2
公开(公告)日：2022-07-12
申请号：US16993959
申请日：2020-08-14
Applicant: Micron Technology, Inc.
Inventor： Justin Eno , William A. Melton , Sean S. Eilert
Abstract: Methods, systems, and devices for adaptive parity techniques for a memory device are described. An apparatus, such as a memory device, may use one or more error correction code (ECC) schemes, an error cache, or both to support access operations. The memory device may receive a command from a host device to read or write data. If the error cache includes an entry for the data, the memory device may read or write the data using a first ECC scheme. If the error cache does not include an entry for the data, the memory device may read or write the data without using an ECC scheme or using a second ECC scheme different than the first ECC scheme.
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公开(公告)号：US11302407B2
公开(公告)日：2022-04-12
申请号：US17202205
申请日：2021-03-15
Applicant: Micron Technology, Inc.
Inventor： Jeffrey L. McVay , Samuel E. Bradshaw , Justin Eno
Abstract: Exemplary methods, apparatuses, and systems include a controller to manage memory proximity disturb. The controller identifies a first memory location in response to an access of a second memory location, the first memory location storing a first value. The controller updates a first disturb value by a first amount, the first disturb value representing a cumulative disturb effect on the first value in the first memory location by accesses to a first plurality of memory locations proximate to the first memory location, the first plurality of memory locations including the second memory location.
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公开(公告)号：US11055167B2
公开(公告)日：2021-07-06
申请号：US15979206
申请日：2018-05-14
Applicant: Micron Technology, Inc.
Inventor： Samuel E. Bradshaw , Justin Eno
Abstract: Techniques for remapping portions of a plurality of non-volatile memory (NVM) dice forming a memory domain. A processing device partitions each NVM die into subslice elements comprising respective physical portions of NVM having proximal disturb relationships. The NVM allocation has user subslice elements and spare subslice elements. For the NVM dice forming the memory domain, the processing device performs an error analysis to identify a predetermined number of subslice elements having highest error rates for the memory domain. Identified user subslice elements having the highest error rates, remap to spare subslice elements of the memory domain that were not identified as having the highest error rates to remove subslice element or elements having highest error rates. At least one user subslice element is remapped from a first die of the memory domain to a second die of the memory domain.
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公开(公告)号：US11048597B2
公开(公告)日：2021-06-29
申请号：US15979269
申请日：2018-05-14
Applicant: Micron Technology, Inc.
Inventor： Justin Eno , Samuel E. Bradshaw
Abstract: Exemplary methods, apparatuses, and systems include a controller detecting a trigger to configure a memory. The memory includes a plurality of dice, including two or more spare dice. The controller accesses each die via one of a plurality of channels. The controller accesses a first spare die via a first channel and the second spare die via a second channel. In response to detecting the trigger, the controller maps a plurality of logical units to the plurality of dice, excluding the two spare dice. The mapping includes mapping each logical unit of the plurality of logical units across multiple dice of the plurality of dice, such that a first half of the plurality of logical units reside on dice accessible via channels other than the first channel and a second half of the plurality of logical units reside on dice accessible via channels other than the second channel.
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