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公开(公告)号：US20210110850A1
公开(公告)日：2021-04-15
申请号：US17124582
申请日：2020-12-17
Applicant: Micron Technology, Inc.
Inventor： Matthew D. Rowley
IPC: G11C5/14 , G06F1/30 , G06F1/3234 , G06F1/3296
Abstract: A method of operating a memory sub-system includes receiving an input voltage at a power management (PM) component of a memory sub-system, where the PM component includes a capacitive voltage divider (CVD), a linear voltage regulator (LVR), and a switching voltage regulator (SVR). The method includes determining whether the input voltage corresponds to a low power mode of the memory sub-system and that the input voltage is higher than an uppermost supply voltage at which a memory component of the memory sub-system is configured to operate. The method further includes selectably coupling, responsive to a determination of the low power mode, the CVD and the LVR and sequentially reducing the input voltage by the CVD and the LVR to a supply voltage for the memory component, where the supply voltage is not higher than the uppermost supply voltage at which the memory component is configured to operate.
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公开(公告)号：US20210065822A1
公开(公告)日：2021-03-04
申请号：US17097447
申请日：2020-11-13
Applicant: Micron Technology, Inc.
Inventor： Matthew D. Rowley , Dustin J. Carter
Abstract: A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage.
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公开(公告)号：US10803963B2
公开(公告)日：2020-10-13
申请号：US16596888
申请日：2019-10-09
Applicant: Micron Technology, Inc.
Inventor： Matthew D. Rowley , Michael J. Henderson
Abstract: A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage divider (CVD) coupled to the PMIC. The CVD is configured to receive the primary supply voltage of the memory sub-system as an input and provide a modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the MPSV is not higher than the uppermost PMIC supply voltage.
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公开(公告)号：US20200075108A1
公开(公告)日：2020-03-05
申请号：US16596888
申请日：2019-10-09
Applicant: Micron Technology, Inc.
Inventor： Matthew D. Rowley , Michael J. Henderson
Abstract: A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage divider (CVD) coupled to the PMIC. The CVD is configured to receive the primary supply voltage of the memory sub-system as an input and provide a modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the MPSV is not higher than the uppermost PMIC supply voltage.
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公开(公告)号：US20200075061A1
公开(公告)日：2020-03-05
申请号：US16119564
申请日：2018-08-31
Applicant: Micron Technology, Inc.
Inventor： Matthew D. Rowley
Abstract: A method of operating a memory sub-system includes receiving an input voltage at a power management (PM) component of a memory sub-system, where the PM component includes a capacitive voltage divider (CVD), a linear voltage regulator (LVR), and a switching voltage regulator (SVR). The method includes determining whether the input voltage corresponds to a low power mode of the memory sub-system and that the input voltage is higher than an uppermost supply voltage at which a memory component of the memory sub-system is configured to operate. The method further includes selectably coupling, responsive to a determination of the low power mode, the CVD and the LVR and sequentially reducing the input voltage by the CVD and the LVR to a supply voltage for the memory component, where the supply voltage is not higher than the uppermost supply voltage at which the memory component is configured to operate.
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Patent Agency Ranking
公开(公告)号：US20200066310A1
公开(公告)日：2020-02-27
申请号：US16112442
申请日：2018-08-24
Applicant: Micron Technology, Inc.
Inventor： Matthew D. Rowley
Abstract: A memory sub-system comprises a power management component comprising a plurality of regulators configured to output respective operating voltages for the memory sub-system. The power management component comprises a power management integrated circuit (PMIC) and is configured to monitor voltage levels of the plurality of regulators and prevent an event of the memory sub-system from occurring until the monitored voltage levels of a set of the plurality of regulators are determined to have reached respective threshold voltage levels.
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公开(公告)号：US20200050252A1
公开(公告)日：2020-02-13
申请号：US16059387
申请日：2018-08-09
Applicant: Micron Technology, Inc.
Inventor： Matthew D. Rowley , Adam J. Hieb
Abstract: A power management system includes a memory component storing a plurality of configuration profiles. A plurality of configuration pins are operatively coupled to the memory component. One or more of the plurality of configuration pins receive one or more signals to selectively activate one of the plurality of configuration profiles.
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公开(公告)号：US11815977B2
公开(公告)日：2023-11-14
申请号：US17560790
申请日：2021-12-23
Applicant: Micron Technology, Inc.
Inventor： Matthew D. Rowley
IPC: G06F1/3234 , G11C16/30 , G06F1/26
CPC classification number: G06F1/3275 , G06F1/266 , G11C16/30
Abstract: An apparatus includes a power management integrated circuit (PMIC) and a power translator component coupled to the PMIC. The power translator component supplies power to the PMIC. The power translator component can further receive, from the PMIC, an indication that the PMIC has experienced a thermal event and responsive to receipt of the indication that the PMIC has experienced the thermal event, prevent powering of the PMIC.
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公开(公告)号：US11367490B2
公开(公告)日：2022-06-21
申请号：US17097447
申请日：2020-11-13
Applicant: Micron Technology, Inc.
Inventor： Matthew D. Rowley , Dustin J. Carter
Abstract: A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage.
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公开(公告)号：US11328779B2
公开(公告)日：2022-05-10
申请号：US17097447
申请日：2020-11-13
Applicant: Micron Technology, Inc.
Inventor： Matthew D. Rowley , Dustin J. Carter
Abstract: A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage.
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