公开(公告)号：US11934824B2

公开(公告)日：2024-03-19

申请号：US16841222

申请日：2020-04-06

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Sivagnanam Parthasarathy ,  Shivasankar Gunasekaran ,  Ameen D. Akel

IPC: G06F9/30 ,  G06F7/544

CPC classification number: G06F9/3001 ,  G06F7/5443 ,  G06F9/30032 ,  G06F9/30043

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-parallel way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of a memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.

公开(公告)号：US11693657B2

公开(公告)日：2023-07-04

申请号：US16717890

申请日：2019-12-17

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Sivagnanam Parthasarathy ,  Shivasankar Gunasekaran ,  Ameen D. Akel

IPC: G06F9/38 ,  G11C7/06 ,  G06F9/30 ,  G11C7/10 ,  G11C8/10

CPC classification number: G06F9/3001 ,  G06F9/3893 ,  G11C7/06 ,  G11C7/1096 ,  G11C8/10

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-serial way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of the memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.

公开(公告)号：US11650742B2

公开(公告)日：2023-05-16

申请号：US16573490

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Shivasankar Gunasekaran ,  Ameen D. Akel ,  Hongyu Wang ,  Justin M. Eno ,  Shivam Swami ,  Samuel E. Bradshaw

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06 ,  G06F12/1027

CPC classification number: G06F3/0631 ,  G06F3/0607 ,  G06F3/0673 ,  G06F12/1027

Abstract: A computer system stores metadata that is used to identify physical memory devices that store randomly-accessible data for memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. Stored metadata associates a first address range of the address space with a first memory device, and a second address range of the address space with a second memory device. The operating system manages processes running on the computer system by accessing the stored metadata. This management includes allocating memory based on the stored metadata so that data for a first process is stored in the first memory device, and data for a second process is stored in the second memory device.

公开(公告)号：US20220156201A1

公开(公告)日：2022-05-19

申请号：US17665823

申请日：2022-02-07

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Sean S. Eilert ,  Hongyu Wang ,  Samuel E. Bradshaw ,  Shivasankar Gunasekaran ,  Justin M. Eno ,  Shivam Swami

IPC: G06F12/1009 ,  G06F12/1027

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, data is stored in memory at one or more logical addresses allocated to an application by an operating system. The data is physically stored in a first memory device of a first memory type (e.g., NVRAM). The operating system determines an access pattern for the stored data. In response to determining the access pattern, the data is moved from the first memory device to a second memory device of a different memory type (e.g., DRAM).

公开(公告)号：US20210240398A1

公开(公告)日：2021-08-05

申请号：US17236981

申请日：2021-04-21

Applicant: Micron Technology, Inc.

Inventor： Shivasankar Gunasekaran ,  Samuel E. Bradshaw ,  Justin M. Eno ,  Ameen D. Akel

IPC: G06F3/06 ,  G06F12/0873 ,  G06F11/07

Abstract: A memory sub-system configured to be responsive to a time to live requirement for load commands from a processor. For example, a load command issued by the processor (e.g., SoC) can include, or be associated with, an optional time to live parameter. The parameter requires that the data at the memory address be available within the time specified by the time to live parameter. When the requested data is currently in the lower speed memory (e.g., NAND flash) and not available in the higher speed memory (e.g., DRAM, NVRAM), the memory sub-system can determine that the data cannot be made available with the specified time and optionally skip the operations and return an error response immediately.

公开(公告)号：US20210191875A1

公开(公告)日：2021-06-24

申请号：US17192744

申请日：2021-03-04

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Shivasankar Gunasekaran ,  Hongyu Wang ,  Justin M. Eno

IPC: G06F12/1009 ,  G06F3/06 ,  G06F12/1027 ,  G06F9/50

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, an operating system allocates memory from a namespace for use by an application. The namespace is a logical reference to physical memory devices in which physical addresses are defined. The namespace is bound to a memory type. In response to binding the namespace to the memory type, the operating system adjusts a page table to map a logical memory address in the namespace to a memory device of the memory type.

公开(公告)号：US20210072957A1

公开(公告)日：2021-03-11

申请号：US16888345

申请日：2020-05-29

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Shivasankar Gunasekaran ,  Ameen D. Akel ,  Dmitri Yudanov ,  Sivagnanam Parthasarathy

IPC: G06F7/544 ,  G06F17/16

Abstract: Systems, apparatuses, and methods of operating memory systems are described. Processing-in-memory capable memory devices are also described, and methods of performing fused-multiply-add operations within the same. Bit positions of bits stored at one or more portions of one or more memory arrays, may be accessed via data lines by activating the same or different access lines. A sensing circuit operatively coupled to a data line may be temporarily formed and measured to determine a state (e.g., a count of the number of bits that are a logic “1”) of accessed bit positions of a data line, and state information may be used to determine a computational result.

公开(公告)号：US20240403225A1

公开(公告)日：2024-12-05

申请号：US18807682

申请日：2024-08-16

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Justin M. Eno ,  Sean Stephen Eilert ,  Shivasankar Gunasekaran ,  Hongyu Wang ,  Shivam Swami

IPC: G06F12/1009 ,  G06F12/1027

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. A virtual page is associated with a first memory type. A page table entry is generated to map a virtual address of the virtual page to a physical address in a first memory device of the first memory type. The page table entry is used by a memory management unit to store the virtual page at the physical address.

公开(公告)号：US20240248854A1

公开(公告)日：2024-07-25

申请号：US18604086

申请日：2024-03-13

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Shivasankar Gunasekaran ,  Hongyu Wang ,  Justin M. Eno

IPC: G06F12/1009 ,  G06F3/06 ,  G06F9/50 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0679 ,  G06F9/5016 ,  G06F12/1027

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, an operating system allocates memory from a namespace for use by an application. The namespace is a logical reference to physical memory devices in which physical addresses are defined. The namespace is bound to a memory type. In response to binding the namespace to the memory type, the operating system adjusts a page table to map a logical memory address in the namespace to a memory device of the memory type.

公开(公告)号：US20240192953A1

公开(公告)日：2024-06-13

申请号：US18582520

申请日：2024-02-20

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Sivagnanam Parthasarathy ,  Shivasankar Gunasekaran ,  Ameen D. Akel

IPC: G06F9/30 ,  G06F7/544

CPC classification number: G06F9/3001 ,  G06F7/5443 ,  G06F9/30032 ,  G06F9/30043

Abstract: Methods, apparatuses, and systems for in-or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-parallel way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of a memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.