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124 条记录 (耗时 0.028 秒)

    SELECTIVE COUPLING OF VOLTAGE FEEDS FOR BODY BIAS VOLTAGE IN AN INTEGRATED CIRCUIT DEVICE
    21.
    发明申请
    SELECTIVE COUPLING OF VOLTAGE FEEDS FOR BODY BIAS VOLTAGE IN AN INTEGRATED CIRCUIT DEVICE 有权
    用于集成电路设备中的身体偏置电压的电压馈电的选择性耦合

    公开(公告)号：US20080135905A1

    公开(公告)日：2008-06-12

    申请号：US12033840

    申请日：2008-02-19

    申请人： James B. Burr ,  Robert Fu

    发明人： James B. Burr ,  Robert Fu

    IPC分类号： H01L23/50 ,  G11C5/14

    CPC分类号： H01L29/0646 ,  G11C5/146 ,  H01L21/823493 ,  H01L21/823892 ,  H01L23/481 ,  H01L27/0203 ,  H01L27/0222 ,  H01L27/0928 ,  H01L29/1095 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be provided. The first pad is for receiving an externally applied body bias voltage. Circuitry for producing a body bias voltage can be coupled to the first pad for coupling a body bias voltage to a plurality of biasing wells disposed on the integrated circuit device. If an externally applied body bias voltage is not provided, the resistive structure automatically couples a power supply voltage to the biasing wells. The power supply voltage may be obtained internally to the integrated circuit.

    摘要翻译： 一种具有体偏置电压机构的集成电路器件。 集成电路包括设置在其中的电阻结构，用于选择性地将外部体偏置电压或电源电压耦合到偏置阱。 可以可选地提供用于与第一外部设置的销连接的第一垫。 第一个焊盘用于接收外部施加的主体偏置电压。 用于产生体偏置电压的电路可以耦合到第一焊盘，用于将体偏置电压耦合到设置在集成电路器件上的多个偏置阱。 如果没有提供外部施加的体偏置电压，则电阻结构自动将电源电压耦合到偏置阱。 电源电压可以在集成电路内部获得。

    Back-biased MOS device fabrication method
    22.
    发明授权
    Back-biased MOS device fabrication method 有权
    背偏MOS器件制造方法

    公开(公告)号：US06838328B1

    公开(公告)日：2005-01-04

    申请号：US10683957

    申请日：2003-10-10

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H01L21/761 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/425

    CPC分类号： H01L21/823892 ,  H01L21/761 ,  H01L21/823878 ,  H01L27/092

    摘要： A plurality of p-wells and n-wells are formed in a front side of a bulk material, and a plurality of n layers and p layers are alternately formed within the bulk material between a back side of the bulk material and the plurality of n-wells and p-wells. The plurality of n layers are electrically isolated from one another and respectively route different potentials to selected ones of the plurality of n-wells, and likewise, the plurality of p layers are electrically isolated from one another and respectively route different potentials to selected ones of the plurality of p-wells.

    Device including a resistive path to introduce an equivalent RC circuit
    24.
    发明授权
    Device including a resistive path to introduce an equivalent RC circuit 有权

    公开(公告)号：US06781213B2

    公开(公告)日：2004-08-24

    申请号：US10393534

    申请日：2003-03-20

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H01L2900

    CPC分类号： H01L27/092 ,  H01L27/0727 ,  H01L29/1087 ,  H01L29/8605

    摘要： Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

    Method for making die-compensated threshold tuning circuit
    25.
    发明授权
    Method for making die-compensated threshold tuning circuit 失效
    制造芯片补偿阈值调谐电路的方法

    公开(公告)号：US6048746A

    公开(公告)日：2000-04-11

    申请号：US92906

    申请日：1998-06-08

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： G01R31/26 ,  G01R31/27 ,  H01L21/66

    CPC分类号： G01R31/275 ,  G01R31/2621

    摘要： To compensate for process, activity and environmental variations in a semiconductor device, a back-bias potential tuning circuit is formed on a semiconductor die. The tuning circuit tunes a bias potential applied to the semiconductor die to maintain a predetermined ratio between a transistor on-current and a transistor off-current through at least one channel region. Then, a leakage current is measured for multiple transistors formed in the semiconductor die to determine a representative leakage of the semiconductor die. Tuning characteristics of the back-bias potential tuning circuit are then set to match the representative leakage of the semiconductor die.

    摘要翻译： 为了补偿半导体器件中的工艺，活性和环境变化，在半导体管芯上形成背偏电位调谐电路。 调谐电路调节施加到半导体管芯的偏置电位，以保持晶体管导通电流和通过至少一个沟道区域的晶体管截止电流之间的预定比率。 然后，对形成在半导体管芯中的多个晶体管测量泄漏电流，以确定半导体管芯的代表性泄漏。 然后设置背偏电位调谐电路的调谐特性以匹配半导体管芯的代表性泄漏。

    Tunable field plate
    26.
    发明授权
    Tunable field plate 失效
    可调场地板

    公开(公告)号：US5998850A

    公开(公告)日：1999-12-07

    申请号：US28457

    申请日：1998-02-24

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H01L21/762 ,  H01L21/765 ,  H01L27/14

    CPC分类号： H01L21/76202 ,  H01L21/765 ,  Y10S257/921

    摘要： First and second semiconductor devices are separated by a field oxide on a semiconductor substrate, and a field plate is positioned over the field oxide. A leakage detector detects a field leakage current between the first and second semiconductor devices. A field plate generator tunes a potential of said field plate according to a magnitude of the field current detected by the leakage current detector. In this manner, field leakage is optimized, and total dose effects may be monitored for signs of device failure.

    摘要翻译： 第一和第二半导体器件由半导体衬底上的场氧化物分隔开，并且场板位于场氧化物上方。 泄漏检测器检测第一和第二半导体器件之间的场漏电流。 场板发生器根据由漏电流检测器检测的励磁电流的大小调谐所述场板的电位。 以这种方式，对场泄漏进行了优化，并且可以监测总体剂量效应以用于设备故障的迹象。

    Method for forming MOS devices with retrograde pocket regions and counter dopant regions buried in the substrate surface
    27.
    发明授权
    Method for forming MOS devices with retrograde pocket regions and counter dopant regions buried in the substrate surface 失效
    用于形成埋置在衬底表面中的逆行袋区和反掺杂区的MOS器件的方法

    公开(公告)号：US5985727A

    公开(公告)日：1999-11-16

    申请号：US885071

    申请日：1997-06-30

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78

    CPC分类号： H01L29/66659 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/7835

    摘要： Disclosed is a low threshold asymmetric MOS device having a pocket region with a graded concentration profile. The pocket region includes a relatively high dopant atom concentration (of the same conductivity type as the bulk region) abutting either the device's source or its drain along the side of the source or drain that faces the device's channel region. The pocket region's graded concentration profile provides a lower dopant concentration near the substrate surface and an increasing dopant concentration below that surface. This provides a relatively low resistance conduction path through the pocket region, while allowing the device's threshold voltage to be somewhat higher at the pocket region. The asymmetric device can also include a counter dopant region located beneath its substrate surface. This forces current to flow in the substrate but just above the region of high counter dopant concentration, where the resistance is relatively low.

    摘要翻译： 公开了具有分级浓度分布的口袋区域的低阈值非对称MOS器件。 袋区域包括与器件的沟道区域相对的源或漏侧的器件的源极或漏极的相对高的掺杂剂原子浓度（与体区相同的导电类型）。 口袋区域的渐变浓度分布在基底表面附近提供较低的掺杂剂浓度，并且在该表面下方增加的掺杂剂浓度。 这提供了通过袋区域的相对较低的电阻传导路径，同时允许器件的阈值电压在口袋区域稍高一些。 不对称装置还可以包括位于其衬底表面下方的反掺杂剂区域。 这迫使电流在衬底中流动，但刚好高于高对位掺杂剂浓度的区域，其中电阻相对较低。

    Asymmetric low power MOS devices
    28.
    发明授权
    Asymmetric low power MOS devices 失效
    不对称低功耗MOS器件

    公开(公告)号：US5780912A

    公开(公告)日：1998-07-14

    申请号：US675804

    申请日：1996-07-05

    申请人： James B. Burr ,  Michael P. Brassington

    发明人： James B. Burr ,  Michael P. Brassington

    IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/788 ,  H01L29/94

    CPC分类号： H01L29/66659 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/7832 ,  H01L29/7833

    摘要： Low threshold voltage MOS devices having asymmetric halo implants are disclosed herein. An asymmetric halo implant provides a pocket region located under a device's source or drain near where the source (or drain) edge abuts the device's channel region. The pocket region has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. Only the source or drain, not both, have the primary pocket region. An symmetric halo device behaves like two pseudo-MOS devices in series: a "source FET" and a "drain FET." If the pocket implant is located under the source, the source FET will have a higher threshold voltage and a much shorter effective channel length than the drain FET.

    摘要翻译： 本文公开了具有不对称晕轮植入物的低阈值电压MOS器件。 非对称晕轮植入物提供位于器件源极或漏极附近的位于源极（或漏极）边缘靠近器件的沟道区域的口袋区域。 口袋区域具有与器件体积相同的导电类型（尽管具有较高的掺杂剂浓度），当然还有与器件的源极和漏极相反的导电类型。 只有源或漏极，而不是两者都具有初级口袋区域。 一个对称的晕圈器件类似于两个串联的伪MOS器件：“源FET”和“漏极FET”。 如果袋式注入位于源极之下，则源FET将具有比漏极FET更高的阈值电压和更短的有效沟道长度。

    Dynamic clocked inverter latch with reduced charge leakage
    29.
    发明授权
    Dynamic clocked inverter latch with reduced charge leakage 失效
    动态时钟反相器锁存器，减少电荷泄漏

    公开(公告)号：US5606270A

    公开(公告)日：1997-02-25

    申请号：US357607

    申请日：1994-12-16

    申请人： Godfrey P. D'Souza ,  James F. Testa ,  Douglas A. Laird ,  James B. Burr

    发明人： Godfrey P. D'Souza ,  James F. Testa ,  Douglas A. Laird ,  James B. Burr

    IPC分类号： H03K3/356 ,  H03K19/00 ,  H03K19/096 ,  H03K19/20

    CPC分类号： H03K19/0963 ,  H03K19/0016

    摘要： A dynamic clocked inverter latch with reduced charge leakage includes a first node biasing circuit with a P-MOSFET and an N-MOSFET totem-pole-coupled between VDD and an output node, and a second node biasing circuit with another N-MOSFET and another P-MOSFET totem-pole-coupled between the output node and VSS. The first P-MOSFET receives an input data signal and the first N-MOSFET receives a clock signal and in accordance therewith together cause the output node to charge to a charged state having a charge voltage associated therewith. The second N-MOSFET also receives the input data signal while the second P-MOSFET receives the inverse of the clock signal and in accordance therewith together cause the output node to discharge to a discharged state having a discharge voltage associated therewith. During inactive states of the clock signal, the first N-MOSFET becomes reverse-biased by the output node discharge voltage, while during inactive states of the inverse clock signal, the second P-MOSFET becomes reverse-biased by the output node charge voltage, thereby virtually eliminating charge leakage to and from the output node, respectively.

    摘要翻译： 具有减小的电荷泄漏的动态时钟反相器锁存器包括具有P-MOSFET的第一节点偏置电路和VDD与输出节点之间的N-MOSFET图腾柱耦合，以及具有另一N-MOSFET和另一N-MOSFET的第二节点偏置电路 输出节点和VSS之间的P-MOSFET图腾柱耦合。 第一P-MOSFET接收输入数据信号，并且第一N-MOSFET接收时钟信号，并且根据它们一起导致输出节点充电到具有与其相关联的充电电压的充电状态。 第二N-MOSFET还接收输入数据信号，而第二P-MOSFET接收到时钟信号的反相，并且根据它们一起使得输出节点放电到具有与其相关联的放电电压的放电状态。 在时钟信号的非活动状态期间，第一N-MOSFET由输出节点放电电压反向偏置，而在反时钟信号的非活动状态期间，第二P-MOSFET由输出节点充电电压反向偏置， 从而实际上分别消除了来自输出节点的电荷泄漏。