公开(公告)号：US11610736B2

公开(公告)日：2023-03-21

申请号：US17368909

申请日：2021-07-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Daiki Fukunaga ,  Hideaki Tanaka ,  Masahiro Wakashima ,  Daisuke Hamada ,  Hironori Tsutsumi ,  Satoshi Maeno ,  Ryota Aso ,  Koji Moriyama ,  Akihiro Tsuru

IPC: H01G4/12 ,  H01G4/012 ,  H01G4/008 ,  H01G4/232 ,  H01G4/224 ,  H01G4/30

Abstract: An electronic component includes a laminate in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated and external electrodes electrically connected to the internal electrodes. A side margin portion as a region in which the plurality of internal electrodes is not provided when a section of the laminate having the length direction and the width direction is viewed from the laminating direction includes a plurality of side margin layers laminated in the width direction. An outer layer portion as a region in which the plurality of internal electrodes is not provided except for the side margin portion when a section of the laminate including the laminating direction and the width direction is viewed from the length direction includes a plurality of layer-margin layers laminated in the laminating direction.

公开(公告)号：US11600446B2

公开(公告)日：2023-03-07

申请号：US17131888

申请日：2020-12-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuta Kurosu ,  Yuta Saito ,  Masahiro Wakashima ,  Daiki Fukunaga ,  Yu Tsutsui

IPC: H01G4/30 ,  H01G4/232 ,  H01G4/248 ,  H01G4/12 ,  H01G4/008

Abstract: A multilayer ceramic capacitor includes a second alloy portion including one metal element provided in a greatest amount among metal elements of an internal electrode layer, and one or more metal elements among a metal group including Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, and Y is provided between a second dielectric ceramic layer and a first internal electrode layer, and between a second dielectric ceramic layer and a second internal electrode layer, respectively.

公开(公告)号：US11508524B2

公开(公告)日：2022-11-22

申请号：US17131891

申请日：2020-12-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuta Kurosu ,  Yuta Saito ,  Masahiro Wakashima ,  Daiki Fukunaga ,  Yu Tsutsui

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/008 ,  C04B35/468 ,  H01G4/12

Abstract: In a multilayer ceramic capacitor, an intersection of an interface is defined by a second dielectric ceramic layer, a first internal electrode layer or a second internal electrode layer, and a third dielectric ceramic layer, on a plane including a length direction and a width direction, the second dielectric ceramic layer and the third dielectric ceramic layer include a near intersection region at or near the intersection, and an average particle size of dielectric particles in the near intersection region is smaller than average particle sizes of dielectric particles in the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer.

公开(公告)号：US11373810B2

公开(公告)日：2022-06-28

申请号：US17131896

申请日：2020-12-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuta Saito ,  Yuta Kurosu ,  Masahiro Wakashima ,  Daiki Fukunaga ,  Yu Tsutsui

IPC: H01G4/30 ,  H01G4/248 ,  H01G4/12 ,  H01G4/232

Abstract: In a multilayer ceramic capacitor, a first segregation defined by at least one metal element selected from a group consisting of Mg, Mn, and Si is present at each of an end in a length direction of a first internal electrode layer not connected to a second external electrode and an end in a length direction of a second internal electrode layer not connected to a first external electrode. A second segregation defined by at least one metal element selected from a group consisting of Mg, Mn, and Si is present at each of an end of the first internal electrode layer in a width direction and an end of the second internal electrode layer in the width direction.

公开(公告)号：US11120945B2

公开(公告)日：2021-09-14

申请号：US16793041

申请日：2020-02-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hideaki Tanaka ,  Daiki Fukunaga ,  Koji Moriyama

IPC: H01G4/005 ,  H01G4/232 ,  H01G4/30 ,  H01G4/12

Abstract: A multilayer ceramic capacitor includes a laminated body and first and second external electrodes respectively on both end surfaces of the laminated body. When regions where first internal electrodes or second internal electrodes are not present are regarded as side margin portions in a cross section of the laminated body as viewed from the laminating direction, the side margin portions include multiple side margin layers, and the content of Si in the side margin layer closest to the internal electrode is lower than that in the side margin layer other than the side margin layer closest to the internal electrode.

公开(公告)号：US10600575B2

公开(公告)日：2020-03-24

申请号：US16285286

申请日：2019-02-26

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hideaki Tanaka ,  Daiki Fukunaga ,  Koji Moriyama

IPC: H01G4/005 ,  H01G4/232 ,  H01G4/30 ,  H01G4/12

Abstract: A multilayer ceramic capacitor includes a laminated body and first and second external electrodes respectively on both end surfaces of the laminated body. When regions where first internal electrodes or second internal electrodes are not present are regarded as side margin portions in a cross section of the laminated body as viewed from the laminating direction, the side margin portions include multiple side margin layers, and the content of Si in the side margin layer closest to the internal electrode is lower than that in the side margin layer other than the side margin layer closest to the internal electrode.

公开(公告)号：US09812260B2

公开(公告)日：2017-11-07

申请号：US15415986

申请日：2017-01-26

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Daiki Fukunaga ,  Hideaki Tanaka ,  Koji Moriyama

IPC: H01G4/30 ,  H01G4/248 ,  H01G4/012 ,  H01G4/12

CPC classification number: H01G4/30 ,  H01G4/005 ,  H01G4/012 ,  H01G4/1218 ,  H01G4/1227 ,  H01G4/248

Abstract: A multilayer ceramic capacitor includes a ceramic body and external electrodes provided on opposite end surfaces of the ceramic body. The ceramic body includes an inner layer portion including a plurality of ceramic layers defining inner layers and a plurality of first and second internal electrodes each disposed at an interface of adjacent ones of the ceramic layers defining the inner layers, outer layer portions sandwiching the inner layer portion in a direction in which the layers are stacked, and side margin portions sandwiching the inner layer portion and the outer layer portions in a widthwise direction. The side margin portion includes pores that decrease in number along a direction from inside to outside of the ceramic body.

公开(公告)号：US11875949B2

公开(公告)日：2024-01-16

申请号：US17844980

申请日：2022-06-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Daiki Fukunaga

IPC: H01G4/30 ,  H01G4/12 ,  H01G4/012 ,  H01G4/232

CPC classification number: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232

Abstract: A method of manufacturing an electronic component includes preparing an unfired multilayer body including first and second main surfaces facing each other in a stacking direction, first and second side surfaces facing each other in a width direction, and first and second end surfaces facing each other in a length direction, bonding one main surface of the unfired multilayer body to an elongated first adhesive sheet, conveying the first adhesive sheet in a first direction in which the first adhesive sheet approaches an elongated second adhesive sheet, and bonding one side surface of the unfired multilayer body to the second adhesive sheet, conveying the second adhesive sheet in a second direction different from the first direction to peel off the unfired multilayer body from the first adhesive sheet, polishing another side surface of the unfired multilayer body, and forming a first insulating layer on the polished another side surface.

公开(公告)号：US11094462B2

公开(公告)日：2021-08-17

申请号：US16656703

申请日：2019-10-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Daiki Fukunaga ,  Hideaki Tanaka

IPC: H01G4/30 ,  H01G4/12 ,  H01G4/232

Abstract: A multilayer ceramic electronic component includes a laminate, a first external electrode on a first end surface of the laminate, and a second external electrode on a second end surface of the laminate. The laminate includes a central layer portion in which each first internal electrode layer and each second internal electrode layer oppose each other with a dielectric ceramic layer therebetween, peripheral layer portions sandwiching the central layer portion in a lamination direction, and side margins sandwiching the central layer portion and the peripheral layer portions in a width direction. The side margins each include multiple ceramic layers laminated in the width direction, and the ceramic layers include an inner layer disposed closest to the laminate and an outer layer disposed farthest from the laminate.

公开(公告)号：US10453615B2

公开(公告)日：2019-10-22

申请号：US15715196

申请日：2017-09-26

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Daiki Fukunaga ,  Masatsugu Kato

IPC: H01G9/00 ,  H01G4/30 ,  H01G4/12 ,  H01G4/005 ,  H01G13/00 ,  H01G4/232

Abstract: A method for manufacturing a multilayer ceramic electronic component includes preparing a laminate including internal electrodes stacked through a ceramic green sheet, the internal electrodes being exposed on a surface of the laminate, heating a functional sheet while the functional sheet is in contact with a predetermined surface of the laminate, on which the internals electrode are exposed, cooling the heated functional sheet, and forming a covering layer formed of the functional sheet on the predetermined surface of the laminate by punching out the functional sheet having been cooled with the laminate.