公开(公告)号：US20150206577A1

公开(公告)日：2015-07-23

申请号：US14162639

申请日：2014-01-23

Applicant: Nvidia Corporation

Inventor： Haiyan Gong ,  Lei Wang ,  Sing-Rong Li ,  Hwong-Kwo Lin ,  Pai-Yi Chang

IPC: G11C11/419 ,  G11C5/14

CPC classification number: G11C11/419 ,  G11C5/147

Abstract: A hybrid write-assist memory system includes an array voltage supply and a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply. Additionally, the hybrid write-assist memory system includes a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply voltage during a write operation. Also, the hybrid write-assist memory system includes a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently with the voltage reduction of the separable cell supply voltage during the write operation. A method of operating a hybrid write-assist memory system is also provided.

Abstract translation: 混合写入辅助存储器系统包括阵列电压源和由位线和字线控制的静态随机存取存储器（SRAM）单元，并采用耦合到阵列电压源的可分离单元电源电压。 此外，混合写入辅助存储器系统包括耦合到SRAM单元的电源电压下降单元，并且在写入操作期间提供可分离单元电源电压的电压降低。 此外，混合写辅助存储器系统包括负位线单元，其耦合到电源电压下降单元，并且在写操作期间与可分离单元电源电压的电压降低同时提供负位线电压。 还提供了一种操作混合写入辅助存储器系统的方法。

公开(公告)号：US20150206576A1

公开(公告)日：2015-07-23

申请号：US14160706

申请日：2014-01-22

Applicant: Nvidia Corporation

Inventor： Haiyan Gong ,  Lei Wang ,  Sing-Rong Li ,  Hwong-Kwo Lin ,  Pai-Yi Chang

IPC: G11C11/419 ,  G11C5/14 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C7/12

Abstract: A negative bit line write assist system includes an array voltage supply and a static random access memory (SRAM) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the SRAM cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation. A negative bit line write assist method is also provided.

Abstract translation: 负位线写入辅助系统包括阵列电压源和静态随机存取存储器（SRAM）单元，其在写入操作期间耦合到阵列电压源并由位线控制。 此外，负位线写入辅助系统包括耦合到SRAM单元的位线电压单元，其中通过写入辅助命令来控制分布电容，以在写入操作期间提供负位线电压的产生。 还提供了一种负位线写入辅助方法。

公开(公告)号：US20150103584A1

公开(公告)日：2015-04-16

申请号：US14054313

申请日：2013-10-15

Applicant: Nvidia Corporation

Inventor： Hwong-Kwo Lin ,  Lei Wang ,  Spencer Gold ,  Zhenye Jiang

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/417 ,  G11C29/022 ,  G11C29/028

Abstract: A configurable delay circuit and a method of clock buffering. One embodiment of the configurable delay circuit includes: (1) a first delay stage electrically couplable in series to a second delay stage, the first delay stage and the second delay stage each having an input port electrically coupled to a signal source, and (2) a delay path select circuit electrically coupled between the first delay stage and the second delay stage, and operable to select between a delay path including the first delay stage and another delay path including the first delay stage and the second delay stage.

Abstract translation: 可配置的延迟电路和时钟缓冲的方法。 可配置延迟电路的一个实施例包括：（1）与第二延迟级串联电耦合的第一延迟级，第一延迟级和第二延迟级各自具有电耦合到信号源的输入端，以及（2 ）电耦合在所述第一延迟级和所述第二延迟级之间的延迟路径选择电路，并且可操作以在包括所述第一延迟级的延迟路径和包括所述第一延迟级和所述第二延迟级的另一延迟路径之间进行选择。

公开(公告)号：US20140347916A1

公开(公告)日：2014-11-27

申请号：US13901614

申请日：2013-05-24

Applicant: NVIDIA Corporation

Inventor： Jun Yang ,  Hwong-Kwo Lin ,  Ju Shen ,  Yong Li ,  Hua Chen

IPC: G11C11/412 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C11/419

Abstract: Disclosed are devices, systems and/or methods relating to an eight transistor (8T) static random access memory (SRAM) cell, according to one or more embodiments. In one embodiment, an SRAM storage cell is disclosed comprising a word line, a write column select line, a cross-coupled data latch, and a first NMOS switch device serially coupled to a second NMOS switch device. In this embodiment, the gate node of the first NMOS switch device is coupled to the word line, a source node of the first NMOS switch device is coupled to the cross-coupled data latch, a gate node of the second NMOS switch device is coupled to the write column select line, and a source node of the second NMOS switch device is coupled to the cross-coupled data latch.

Abstract translation: 公开了根据一个或多个实施例的与八晶体管（8T）静态随机存取存储器（SRAM）单元相关的器件，系统和/或方法。 在一个实施例中，公开了一种SRAM存储单元，其包括字线，写列选择线，交叉耦合数据锁存器和串联耦合到第二NMOS开关器件的第一NMOS开关器件。 在该实施例中，第一NMOS开关器件的栅极节点耦合到字线，第一NMOS开关器件的源节点耦合到交叉耦合数据锁存器，第二NMOS开关器件的栅极节点被耦合 到写列选择线，并且第二NMOS开关器件的源节点耦合到交叉耦合数据锁存器。

公开(公告)号：US08866528B2

公开(公告)日：2014-10-21

申请号：US13668110

申请日：2012-11-02

Applicant: NVIDIA Corporation

Inventor： Hwong-Kwo Lin ,  Ge Yang ,  Xi Zhang ,  Jiani Yu ,  Ting-Hsiang Chu

IPC: H03K3/289

CPC classification number: H03K3/356156 ,  G01R31/318541 ,  H03K3/356121

Abstract: A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit comprises a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels and a dock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal. The second flip-flop sub-circuit is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal. The second flip-flop sub-circuit comprises a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions.

Abstract translation: 双触发器电路将两个或更多个触发器子电路组合成单个电路。 触发器电路包括第一触发器子电路和第二触发器子电路。 第一触发器子电路包括第一存储子电路，其被配置为存储第一选择的输入信号，并且当缓冲的时钟信号在两个不同逻辑电平之间转换时，将第一选定的输入信号传送到第一输出信号， 被配置为接收时钟输入信号，产生反相时钟信号，并产生缓冲的时钟信号。 第二触发器子电路耦合到时钟驱动器并且被配置为接收反相时钟信号和经缓冲的时钟信号。 第二触发器子电路包括第二存储子电路，其被配置为存储第二选择的输入信号，并且在缓冲的时钟信号转换时将第二选定输入信号传送到第二输出信号。

公开(公告)号：US20140167828A1

公开(公告)日：2014-06-19

申请号：US13715969

申请日：2012-12-14

Applicant: NVIDIA CORPORATION

Inventor： Ge Yang ,  Hwong-Kwo Lin ,  Xi Zhang ,  Jiani Yu

IPC: H03K3/037

CPC classification number: H03K3/0375

Abstract: Small area low power data retention flop. In accordance with a first embodiment of the present invention, a circuit includes a master latch coupled to a data retention latch. The data retention latch is configured to operate as a slave latch to the master latch to implement a master-slave flip flop during normal operation. The data retention latch is configured to retain an output value of the master-slave flip flop during a low power data retention mode when the master latch is powered down. A single control input is configured to select between the normal operation and the low power data retention mode. The circuit may be independent of a third latch.

Abstract translation: 小区域低功率数据保留触发器。 根据本发明的第一实施例，电路包括耦合到数据保持锁存器的主锁存器。 数据保持锁存器被配置为作为从锁存器操作到主锁存器，以在正常操作期间实现主从触发器。 数据保持锁存器配置为在主器件锁存器掉电时，在低功耗数据保持模式期间保持主从触发器的输出值。 单个控制输入被配置为在正常操作和低功率数据保持模式之间进行选择。 电路可以独立于第三锁存器。