公开(公告)号：US20240168795A1

公开(公告)日：2024-05-23

申请号：US18081552

申请日：2022-12-14

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Olivier Giroux ,  Jack H. Choquette ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Rui Guo ,  Chao Li ,  Vishalkumar Ketankumar Mehta ,  David Dastous St. Hilaire ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Ronny Meir Krashinsky ,  Subhasmita Chakraborty ,  Vikram Dhar

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F9/54

CPC classification number: G06F9/467 ,  G06F9/3004 ,  G06F9/3877 ,  G06F9/541

Abstract: Apparatuses, systems, and techniques to perform delayed memory transaction information check. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to check for information provided by one or more users about one or more memory transactions after a timeout event indicated by one or more users.

公开(公告)号：US20240168763A1

公开(公告)日：2024-05-23

申请号：US18072300

申请日：2022-11-30

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Kyrylo Perelygin ,  Maciej Tyrlik ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Balaji Krishna Yugandhar Atukuri ,  Rishkul Kulkarni ,  Konstantinos Kyriakopoulos ,  Edward H. Gornish ,  David Allan Berson ,  Bageshri Sathe ,  James Player ,  Aman Arora ,  Alan Kaatz ,  Andrew Kerr ,  Haicheng Wu ,  Cris Cecka ,  Vijay Thakkar ,  Sean Treichler ,  Jack H. Choquette ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Ronny Meir Krashinsky ,  Cody Addison ,  Girish Bhaskarrao Bharambe

IPC: G06F9/30 ,  G06F17/16

CPC classification number: G06F9/3001 ,  G06F17/16

Abstract: Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause two or more other computational operations to be performed by two or more streaming multiprocessors (SMs).

公开(公告)号：US20240168762A1

公开(公告)日：2024-05-23

申请号：US18072081

申请日：2022-11-30

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Kyrylo Perelygin ,  Maciej Tyrlik ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Balaji Krishna Yugandhar Atukuri ,  Rishkul Kulkarni ,  Konstantinos Kyriakopoulos ,  Edward H. Gornish ,  David Allan Berson ,  Bageshri Sathe ,  James Player ,  Aman Arora ,  Alan Kaatz ,  Andrew Kerr ,  Haicheng Wu ,  Cris Cecka ,  Vijay Thakkar ,  Sean Treichler ,  Jack H. Choquette ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Ronny Meir Krashinsky ,  Cody Addison ,  Girish Bhaskarrao Bharambe

IPC: G06F9/30 ,  G06F17/16

CPC classification number: G06F9/3001 ,  G06F9/3009 ,  G06F17/16

Abstract: Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause one or more other computational operations to wait until a portion of matrix multiply-accumulate (MMA) operations have been performed.

公开(公告)号：US20240168659A1

公开(公告)日：2024-05-23

申请号：US18086429

申请日：2022-12-21

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Stephen Anthony Bernard Jones ,  Alexander Lev Minkin ,  Olivier Giroux ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Chao Li ,  Ronny Meir Krashinsky ,  Alan Kaatz ,  Andrew Robert Kerr ,  Jack H. Choquette

IPC: G06F3/06 ,  G06F12/0862

CPC classification number: G06F3/0625 ,  G06F3/0646 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0862 ,  G06F2212/608

Abstract: Apparatuses, systems, and techniques to transform and store information corresponding to one or more memory transactions. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information corresponding to one or more memory transactions resulting from performance of the API to be transformed and stored.

公开(公告)号：US20240118899A1

公开(公告)日：2024-04-11

申请号：US18105679

申请日：2023-02-03

Applicant: NVIDIA Corporation

Inventor： Aditya Avinash Atluri ,  Jack Choquette ,  Carter Edwards ,  Olivier Giroux ,  Praveen Kumar Kaushik ,  Ronny Krashinsky ,  Rishkul Kulkarni ,  Konstantinos Kyriakopoulos

IPC: G06F9/38

CPC classification number: G06F9/3851

Abstract: Apparatuses, systems, and techniques to adapt instructions in a SIMT architecture for execution on serial execution units. In at least one embodiment, a set of one or more threads is selected from a group of active threads associated with an instruction and the instruction is executed for the set of one or more threads on a serial execution unit.

公开(公告)号：US20230305845A1

公开(公告)日：2023-09-28

申请号：US17710699

申请日：2022-03-31

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Stephen Anthony Bernard Jones ,  David Anthony Fontaine ,  Sebastian Piotr Jodlowski ,  Aditya Avinash Atluri ,  Andrew Robert Kerr ,  Michael Andrew Clark ,  Gonzalo Brito Gadeschi ,  Olivier Giroux ,  Jaydeep Marathe ,  Thibaut Lutz ,  Hariharan Sandanagobalane ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Girish Bhaskarrao Bharambe ,  Rishkul Kulkarni ,  Konstantinos Kyriakopoulos

IPC: G06F9/30 ,  G06F9/54 ,  G06F9/50

CPC classification number: G06F9/3009 ,  G06F9/30043 ,  G06F9/544 ,  G06F9/5016

Abstract: Apparatuses, systems, and techniques to cause data to be selectively stored in one or more memory locations. In at least one embodiment, a processor is to cause data to be selectively stored in one or more memory locations based, at least in part, on one or more threads to use the data.

公开(公告)号：US20230297643A1

公开(公告)日：2023-09-21

申请号：US17700239

申请日：2022-03-21

Applicant: NVIDIA Corporation

Inventor： Aniket Shivam ,  Andrew Kerr ,  Haicheng Wu ,  Manish Gupta ,  Nikita Shustrov ,  Qing Yang ,  Alan Kaatz ,  Aditya Avinash Atluri

IPC: G06F17/16 ,  G06F7/483

CPC classification number: G06F17/16 ,  G06F7/483

Abstract: Matrix multiplication operations can be implemented, at least in part, on one or more tensor cores of a parallel processing unit. An efficiency of the matrix multiplication operations can be improved in cases where one of the input operands or the output operand of the matrix multiplication operation is a square matrix having a triangular data pattern. In such cases, the number of computations performed by the tensor cores of the parallel processing unit can be reduced by dropping computations and/or masking out elements of the square matrix input operand on one side of the main diagonal of the square matrix. In other cases where the output operand exhibits the triangular data pattern, computations can be dropped or masked out for the invalid side of the main diagonal of the square matrix. In an embodiment, a library implementing the matrix multiplication operations is provided.