利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

113 条记录 (耗时 0.038 秒)

    Schottky Electrode of Nitride Semiconductor Device and Process for Production Thereof
    21.
    发明申请
    Schottky Electrode of Nitride Semiconductor Device and Process for Production Thereof 审中-公开
    氮化硅半导体器件的肖特基电极及其制造方法

    公开(公告)号：US20080006853A1

    公开(公告)日：2008-01-10

    申请号：US11571816

    申请日：2005-07-08

    申请人： Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Okamoto ,  Masaaki Kuzuhara ,  Takashi Inoue ,  Koji Hataya

    发明人： Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Okamoto ,  Masaaki Kuzuhara ,  Takashi Inoue ,  Koji Hataya

    IPC分类号： H01L29/47 ,  H01L21/283 ,  H01L29/812

    CPC分类号： H01L29/475 ,  H01L29/2003 ,  H01L29/812

    摘要： The present invention provides a Schottky electrode for a nitride semiconductor device having a high barrier height, a low leak current performance and a low resistance and being thermally stable, and a process for production thereof. The Schottky electrode for a nitride semiconductor has a layered structure that comprises a copper (Cu) layer being in contact with the nitride semiconductor and a first electrode material layer formed on the copper (Cu) layer as an upper layer. As the first electrode material, a metal material which has a thermal expansion coefficient smaller than the thermal expansion coefficient of copper (Cu) and starts to undergo a solid phase reaction with copper (Cu) at a temperature of 400° C. or higher is employed.

    摘要翻译： 本发明提供了一种用于氮化物半导体器件的肖特基电极，其具有高势垒高度，低漏电流性能和低电阻并且是热稳定的，以及其制造方法。 用于氮化物半导体的肖特基电极具有包括与氮化物半导体接触的铜（Cu）层和形成在作为上层的铜（Cu）层上的第一电极材料层的层状结构。 作为第一电极材料，在400℃以上的温度下开始与铜（Cu）的热膨胀系数小于铜（Cu）的热膨胀系数并开始与铜（Cu）的固相反应的金属材料为 雇用。

    Field Effect Transistor
    26.
    发明申请
    Field Effect Transistor 审中-公开
    场效应晶体管

    公开(公告)号：US20090173968A1

    公开(公告)日：2009-07-09

    申请号：US12097700

    申请日：2006-12-12

    申请人： Kouji Matsunaga ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Akio Wakejima ,  Yuji Ando ,  Hironobu Miyamoto ,  Takashi Inoue ,  Yasuhiro Murase

    发明人： Kouji Matsunaga ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Akio Wakejima ,  Yuji Ando ,  Hironobu Miyamoto ,  Takashi Inoue ,  Yasuhiro Murase

    IPC分类号： H01L29/205

    CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/66462

    摘要： A semiconductor device 100 contains an undoped GaN channel layer 105, an AlGaN electron donor layer 106 provided on the undoped GaN channel layer 105 as being brought into contact therewith, an undoped GaN layer 107 provided on the AlGaN electron donor layer 106, a source electrode 101 and a drain electrode 103 provided on the undoped GaN layer 107 as being spaced from each other, a recess 111 provided in the region between the source electrode 101 and the drain electrode 103, as being extended through the undoped GaN layer 107, a gate electrode 102 buried in the recess 111 as being brought into contact with the AlGaN electron donor layer 106 on the bottom surface thereof, and an SiN film 108 provided on the undoped GaN layer 107, in the region between the gate electrode 102 and the drain electrode 103.

    摘要翻译： 半导体器件100包含未掺杂的GaN沟道层105，设置在与其接触的未掺杂的GaN沟道层105上的AlGaN电子供体层106，设置在AlGaN电子供体层106上的未掺杂的GaN层107，源电极 101和设置在未掺杂的GaN层107上彼此间隔开的漏电极103，设置在源电极101和漏电极103之间的区域中的凹槽111延伸穿过未掺杂的GaN层107，栅极 埋入凹槽111中的电极102与其底表面上的AlGaN电子供体层106接触，以及设置在未掺杂的GaN层107上的SiN膜108，在栅电极102和漏极之间的区域 103。

    Bipolar transistor
    28.
    发明授权
    Bipolar transistor 有权
    双极晶体管

    公开(公告)号：US08716835B2

    公开(公告)日：2014-05-06

    申请号：US13124873

    申请日：2009-10-16

    申请人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Kazuki Ota

    发明人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Kazuki Ota

    IPC分类号： H01L29/66 ,  H01L29/737 ,  H01L29/20

    CPC分类号： H01L29/7371 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/475 ,  H01L29/66318

    摘要： A bipolar transistor is provided with an emitter layer, a base layer and a collector layer. The emitter layer is formed above a substrate and is an n-type conductive layer including a first nitride semiconductor. The base layer is formed on the emitter layer and is a p-type conductive including a second nitride semiconductor. The collector layer is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed such that a crystal growth direction to the substrate surface is parallel to a substrate direction of [000-1]. The third nitride semiconductor contains InycAlxcGa1-xc-ycN (0•xc•1, 0•yc•1, 0

    摘要翻译： 双极晶体管设置有发射极层，基极层和集电极层。 发射极层形成在衬底之上，并且是包括第一氮化物半导体的n型导电层。 基极层形成在发射极层上，是包含第二氮化物半导体的p型导体。 集电极层形成在基极层上并且包括第三氮化物半导体。 形成集电体层，基极层和发射极层，使得到基板表面的晶体生长方向平行于[000-1]的基板方向。 第三氮化物半导体含有InycAlxcGa1-xc-ycN（0·xc·1,0,0·yc·1,0,0cc·yc·1）。 第三氮化物半导体中的表面侧的a轴长度比基板侧的a轴长短。

    Semiconductor device using a group III nitride-based semiconductor
    29.
    发明授权
    Semiconductor device using a group III nitride-based semiconductor 有权
    使用III族氮化物基半导体的半导体器件

    公开(公告)号：US08674407B2

    公开(公告)日：2014-03-18

    申请号：US12919640

    申请日：2009-03-12

    申请人： Yuji Ando ,  Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

    发明人： Yuji Ando ,  Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

    IPC分类号： H01L29/66

    CPC分类号： H01L29/7783 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/7785

    摘要： The present invention provides a semiconductor device having such a structure formed by sequentially laminating a lower barrier layer composed of lattice-relaxed AlxGa1-xN (0≦x≦1), a channel layer composed of InyGa1-yN (0≦y≦1) with compressive strain and a contact layer composed of AlzGa1-zN (0≦z≦1), wherein a two-dimensional electron gas is produced in the vicinity of an interface of said InyGa1-yN channel layer with said AlzGa1-zN contact layer; a gate electrode is formed so as to be embedded in the recessed portion with intervention of an insulating film, which recessed portion is formed by removing a part of said AlzGa1-zN contact layer by etching it away until said InyGa1-yN channel layer is exposed; and, ohmic electrodes are formed on the AlzGa1-zN contact layer. Thus, the semiconductor device has superior uniformity and reproducibility of the threshold voltage while maintaining a low gate leakage current, and is also applicable to the enhancement mode type.

    摘要翻译： 本发明提供一种具有这样的结构的半导体器件，该半导体器件通过依次层叠由晶格弛豫的Al x Ga 1-x N（0 @ x @ 1）构成的下阻挡层，由InyGa1-yN（0 @ y @ 1） 具有压应变和由Al z Ga 1-z N（0 @ z @ 1）组成的接触层，其中在所述In y Ga 1-y N沟道层与所述Al z Ga 1-z N接触层的界面附近产生二维电子气; 通过介入绝缘膜形成嵌入在凹陷部分中的栅电极，该凹陷部分通过蚀刻除去所述AlzGa1-zN接触层的一部分而形成，直到所述In y Ga 1-y N沟道层暴露 ; 并且在AlzGa1-zN接触层上形成欧姆电极。 因此，半导体器件在保持低栅极漏电流的同时具有优异的阈值电压的均匀性和再现性，并且也适用于增强型。

    Semiconductor device
    30.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08525229B2

    公开(公告)日：2013-09-03

    申请号：US12299542

    申请日：2007-05-07

    申请人： Yasuhiro Okamoto ,  Yuji Ando ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

    发明人： Yasuhiro Okamoto ,  Yuji Ando ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

    IPC分类号： H01L29/205 ,  H01L29/778

    CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/42316

    摘要： A semiconductor device includes a channel layer, an electron-supplying layer provided on the channel layer, a cap layer provided on the electron-supplying layer and creating lattice match with the channel layer, and ohmic electrodes provided on the cap layer. The cap layer has a composition of (InyAl1-y)zGa1-zN (0≦y≦1, 0≦z≦1). The z for such cap layer monotonically decreases as being farther away from the electron-supplying layer.

    摘要翻译： 半导体器件包括沟道层，设置在沟道层上的电子供给层，设置在电子供给层上并与沟道层形成晶格匹配的盖层以及设置在盖层上的欧姆电极。 盖层具有（In y Al 1-y）z Ga 1-z N（0 @ y @ 1，0 @ z @ 1）的组成。 这种盖层的z随着远离电子供应层而单调减小。