公开(公告)号：US20150371693A1

公开(公告)日：2015-12-24

申请号：US14310269

申请日：2014-06-20

Applicant: Oracle International Corporation

Inventor： Robert P. Masleid ,  Don Draper ,  Venkat Krishnaswamy ,  Paul Loewenstein

IPC: G11C8/10 ,  G11C8/06

CPC classification number: G11C8/10 ,  G06F11/1048 ,  G11C7/1006 ,  G11C8/06

Abstract: Embodiments of an apparatus and method for encoding data are disclosed that may allow for reduced simultaneous switching output noise. The apparatus may include a row decode circuit, a column decode circuit, and a memory array. The row decode circuit and column decode circuits may be configured to decode a first portion and a second portion, respectively, of a given data word of a first plurality of data words, where each data word may include N data bits, and where N is an integer greater than one. The memory array may be configured to store a second plurality of data words where each data word may include M data bits, and where M is an integer greater than N. The memory array may be further configured to retrieve a given data word of the second plurality of data words dependent upon the decoded first and second portions.

Abstract translation: 公开了一种用于编码数据的装置和方法的实施例，其可以允许降低的同时开关输出噪声。 该装置可以包括行解码电路，列解码电路和存储器阵列。 行解码电路和列解码电路可以被配置为分别解码第一多个数据字的给定数据字的第一部分和第二部分，其中每个数据字可以包括N个数据位，并且其中N是 大于1的整数。 存储器阵列可以被配置为存储第二多个数据字，其中每个数据字可以包括M个数据位，并且其中M是大于N的整数。存储器阵列还可以被配置为检索第二个数据字的给定数据字 取决于解码的第一和第二部分的多个数据字。

公开(公告)号：US20150194967A1

公开(公告)日：2015-07-09

申请号：US14146852

申请日：2014-01-03

Applicant: Oracle International Corporation

Inventor： Robert P. Masleid

IPC: H03L7/00

CPC classification number: H03L7/00 ,  H03K5/135 ,  H03L7/0814 ,  H03L7/0991 ,  H03L2207/50 ,  H04L7/0338

Abstract: An alignment circuit is disclosed. In one embodiment, the circuit includes a shift register having a plurality of serially-coupled storage elements each configured to receive a first signal on a respective clock input, wherein a data input of a first one of the serially-coupled storage elements is configured to receive a second signal. The circuit further includes a detector configured to detect a position of a logical transition based on data shifted into the shift register and an encoder configured to generate selection signals based on the position of the logical transition. A multiplexer tree configured to select a bit position of one of the plurality of serially-coupled storage elements based on the selection signals, wherein an output of the multiplexer tree is a third signal that is a version of the second signal.

Abstract translation: 公开了一种对准电路。 在一个实施例中，电路包括具有多个串联耦合的存储元件的移位寄存器，每个存储元件被配置为在相应的时钟输入上接收第一信号，其中串行耦合存储元件中的第一个的数据输入被配置为 接收第二个信号。 电路还包括检测器，其被配置为基于移入到移位寄存器中的数据检测逻辑转换的位置;以及编码器，被配置为基于逻辑转换的位置产生选择信号。 多路复用器树，其被配置为基于所述选择信号来选择所述多个串行耦合存储元件中的一个的位位置，其中所述多路复用器树的输出是作为所述第二信号的版本的第三信号。

公开(公告)号：US09036447B2

公开(公告)日：2015-05-19

申请号：US13719773

申请日：2012-12-19

Applicant: Oracle International Corporation

Inventor： Robert P. Masleid ,  Johan Bastiaens

IPC: G11C8/10 ,  G11C8/00

CPC classification number: G11C8/10

Abstract: A decoder circuit with reduced leakage configured to decode an address and drive one of a number of word lines may be implemented with two-high logic gates in a pre-decode stage, a decode stage, and a word line driver stage. Such decoder circuits may include, in the word line driver stage, a number of two-high NOR gates configured to drive one of a number of word lines. In some embodiments, the two-high logic gates that share common inputs are implemented with multi-output static logic.

Abstract translation: 具有减少泄漏的解码器电路被配置为解码地址并驱动多个字线中的一个字线可以在预解码级，解码级和字线驱动级中用两高逻辑门来实现。 这样的解码器电路可以在字线驱动器级中包括配置为驱动多个字线中的一个字线的多个二极NOR门。 在一些实施例中，共享公共输入的两高逻辑门由多输出静态逻辑实现。

公开(公告)号：US20140169117A1

公开(公告)日：2014-06-19

申请号：US13719773

申请日：2012-12-19

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Robert P. Masleid ,  Johan Bastiaens

IPC: G11C8/10

CPC classification number: G11C8/10

Abstract: A decoder circuit with reduced leakage configured to decode an address and drive one of a number of word lines may be implemented with two-high logic gates in a pre-decode stage, a decode stage, and a word line driver stage. Such decoder circuits may include, in the word line driver stage, a number of two-high NOR gates configured to drive one of a number of word lines. In some embodiments, the two-high logic gates that share common inputs are implemented with multi-output static logic.

Abstract translation: 具有减少泄漏的解码器电路被配置为解码地址并驱动多个字线中的一个字线可以在预解码级，解码级和字线驱动级中用两高逻辑门来实现。 这样的解码器电路可以在字线驱动器级中包括配置为驱动多个字线中的一个字线的多个二极NOR门。 在一些实施例中，共享公共输入的两高逻辑门由多输出静态逻辑实现。

公开(公告)号：US20140136912A1

公开(公告)日：2014-05-15

申请号：US13673503

申请日：2012-11-09

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Robert P. Masleid ,  Ali Vahidsafa

IPC: G01R31/3177

CPC classification number: G01R31/318541

Abstract: A combo dynamic flop with scan flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a dynamic latch circuit and a static latch circuit. The dynamic latch circuit includes a dynamic latch storage node. The static latch circuit includes a static storage node driven by the dynamic latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit, a scan storage node, and a scan feed-forward circuit driven from the static latch. The output buffer circuit includes a dynamic latch driver driven from the dynamic latch circuit and a static driver driven from the static latch circuit.

Abstract translation: 具有扫描电路的组合动态触发器包括触发器电路，扫描控制电路和输出缓冲电路。 触发器电路包括动态锁存电路和静态锁存电路。 动态锁存电路包括动态锁存存储节点。 静态锁存电路包括由动态锁存器驱动的静态存储节点。 扫描控制电路包括扫描从机前馈电路，扫描锁存电路和由扫描反馈电路驱动的扫描驱动电路。 扫描锁存电路包括扫描反馈电路，扫描存储节点和从静态锁存器驱动的扫描前馈电路。 输出缓冲电路包括从动态锁存电路驱动的动态锁存驱动器和从静态锁存电路驱动的静态驱动器。