利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

37 条记录 (耗时 0.03 秒)

    NAND-type flash memory device with high voltage PMOS and embedded poly and methods of fabricating the same
    22.
    发明申请
    NAND-type flash memory device with high voltage PMOS and embedded poly and methods of fabricating the same 审中-公开
    具有高压PMOS和嵌入式多晶硅的NAND型闪存器件及其制造方法

    公开(公告)号：US20070133289A1

    公开(公告)日：2007-06-14

    申请号：US11606535

    申请日：2006-11-30

    申请人： Han-Rei Ma ,  Fu-Chang Hsu ,  Peter Lee ,  Xiang Hong

    发明人： Han-Rei Ma ,  Fu-Chang Hsu ,  Peter Lee ,  Xiang Hong

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11546

    摘要： The device of the invention includes a plurality of isolation layers formed at predetermined regions of a semiconductor substrate and running parallel with each other. The devices of the present invention also include a high voltage PMOS placed on top of a deep N-well and NMOS placed above a triple P-well inside the deep N-well in the peripheral area to pass both positive and negative high voltage of around +20V and −20V to the cell area. In one embodiment, the cell array, source lines and bit lines are all placed on top of the P-substrate without a deep N-well or Triple P-well. In other embodiments, the cell array, source lines and bit lines are placed on top of the deep N-well and triple P-well.

    摘要翻译： 本发明的器件包括形成在半导体衬底的预定区域并彼此平行延伸的多个隔离层。 本发明的器件还包括放置在深N阱和NMOS顶部的高电压PMOS，其放置在外围区域的深N阱内的三重P阱上方，以通过周围的正和负高电压 + 20V和-20V到细胞区域。 在一个实施例中，单元阵列，源极线和位线都被放置在P衬底的顶部上，而没有深N阱或三重P阱。 在其他实施例中，将单元阵列，源极线和位线放置在深N阱和三重P阱的顶部。

    Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
    23.
    发明授权
    Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations 有权
    组合非易失性存储器采用统一技术与字节，页面和块写入以及同步读写操作

    公开(公告)号：US07154783B2

    公开(公告)日：2006-12-26

    申请号：US11011306

    申请日：2004-12-14

    申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

    发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

    IPC分类号： G11C16/04

    CPC分类号： H01L27/115 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3445 ,  G11C2216/18 ,  G11C2216/22 ,  H01L27/11521 ,  H01L27/11524

    摘要： A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

    摘要翻译： 描述了组合EEPROM和闪存，其中包含单元，其中闪存单元的堆叠栅极晶体管与选择晶体管结合使用以形成EEPROM单元。 使选择晶体管足够小，以便允许EEPROM单元适应闪存单元的位线间距，这有助于将两个存储器组合成包含两个单元的存储体。 闪存单元被块擦除时，EEPROM单元被字节擦除。 小选择晶体管具有小的沟道长度和宽度，其通过在CHE编程操作期间增加选择晶体管上的栅极电压和预充电位线来补偿。

    Nonvolatile memory with a unified cell structure
    28.
    发明授权
    Nonvolatile memory with a unified cell structure 有权
    具有统一单元结构的非易失性存储器

    公开(公告)号：US07636252B2

    公开(公告)日：2009-12-22

    申请号：US11483241

    申请日：2006-07-07

    申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

    发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

    IPC分类号： G11C16/04

    CPC分类号： H01L27/115 ,  G11C11/005 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

    摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

    摘要翻译： 公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。 此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。 与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。 此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。 该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

    Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
    29.
    发明授权
    Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations 有权
    组合非易失性存储器采用统一技术与字节，页面和块写入以及同步读写操作

    公开(公告)号：US07349257B2

    公开(公告)日：2008-03-25

    申请号：US11633334

    申请日：2006-12-04

    申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

    发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

    IPC分类号： G11C11/34

    CPC分类号： H01L27/115 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3445 ,  G11C2216/18 ,  G11C2216/22 ,  H01L27/11521 ,  H01L27/11524

    摘要： A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

    摘要翻译： 描述了组合EEPROM和闪存，其中包含单元，其中闪存单元的堆叠栅极晶体管与选择晶体管结合使用以形成EEPROM单元。 使选择晶体管足够小，以便允许EEPROM单元适应闪存单元的位线间距，这有助于将两个存储器组合成包含两个单元的存储体。 闪存单元被块擦除时，EEPROM单元被字节擦除。 小选择晶体管具有小的沟道长度和宽度，其通过在CHE编程操作期间增加选择晶体管上的栅极电压和预充电位线来补偿。