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45 条记录 (耗时 0.032 秒)

    Providing high precision resistance in an integrated circuit using a thin film resistor of controlled dimension
    21.
    发明授权
    Providing high precision resistance in an integrated circuit using a thin film resistor of controlled dimension 有权
    使用受控尺寸的薄膜电阻在集成电路中提供高精度电阻

    公开(公告)号：US07005361B2

    公开(公告)日：2006-02-28

    申请号：US10875846

    申请日：2004-06-24

    申请人： Siang Ping Kwok ,  Eric W. Beach ,  Philipp Steinmann

    发明人： Siang Ping Kwok ,  Eric W. Beach ,  Philipp Steinmann

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/0802 ,  H01L28/24

    摘要： In one embodiment, an integrated circuit includes a thin film resistor, which includes a resistor material that has been deposited on a substrate surface within a channel defined by opposing first and second portions of a stencil structure formed on the substrate surface, the resistor material having an initial width determined by a width of the channel. The stencil structure has been adapted to receive a planarizing material that protects against reduction of the initial width of the resistor material during subsequent process steps for removing the stencil structure. A head mask overlays an end portion of the thin film resistor and a dielectric overlays the head mask, the dielectric defining a via formed in the dielectric above a portion of the head mask. A conductive material has been deposited in the via, coupled to the portion of the head mask and electrically connecting the thin film resistor to other components of the integrated circuit.

    摘要翻译： 在一个实施例中，集成电路包括薄膜电阻器，薄膜电阻器包括已经沉积在由形成在衬底表面上的模板结构的相对的第一和第二部分限定的沟道内的衬底表面上的电阻材料，电阻器材料具有 由通道的宽度确定的初始宽度。 模板结构已经适于接收平面化材料，其在随后的去除模版结构的工艺步骤期间防止电阻材料的初始宽度的减小。 头部掩模覆盖薄膜电阻器的端部，并且电介质覆盖头部掩模，所述电介质限定在头罩中的一部分上形成在电介质中的通孔。 导电材料已经沉积在通孔中，耦合到头罩的部分并将薄膜电阻器电连接到集成电路的其它部件。

    One mask solution for the integration of the thin film resistor
    23.
    发明授权
    One mask solution for the integration of the thin film resistor 有权
    一种面膜解决方案，用于整合薄膜电阻

    公开(公告)号：US06497824B1

    公开(公告)日：2002-12-24

    申请号：US09661716

    申请日：2000-09-14

    申请人： Chun-Liang A. Chen ,  Philipp Steinmann ,  Stuart M. Jacobsen

    发明人： Chun-Liang A. Chen ,  Philipp Steinmann ,  Stuart M. Jacobsen

    IPC分类号： B44C122

    CPC分类号： H01L28/24

    摘要： A method for integrating a thin film resistor (60) into an interconnect process flow. Metal interconnect lines (40) are formed over a semiconductor body (10). An interlevel dielectric (50) is then formed over the metal interconnect lines (40). Conductively filled vias (62) are then formed through the interlevel dielectric (50) to the metal interconnect lines (40). A thin film resistor (60) is then formed connecting between at least two of the conductively filled vias (62) using a single mask step. Connection to the resistor (60) is from below using a via process sequence already required for connecting between interconnect layers (40, 64). Thus, only one additional mask step is required to incorporate the resistor (60).

    摘要翻译： 一种将薄膜电阻器（60）集成到互连工艺流程中的方法。 金属互连线（40）形成在半导体本体（10）上。 然后在金属互连线（40）上形成层间电介质（50）。 然后，通过层间电介质（50）将导电填充的通孔（62）形成到金属互连线（40）。 然后使用单个掩模步骤形成在至少两个导电填充的通孔（62）之间连接薄膜电阻器（60）。 使用已经需要连接互连层（40,64）的通孔工艺程序，从下方连接到电阻器（60）。 因此，仅需要一个附加的掩模步骤来结合电阻器（60）。

    METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT
    24.
    发明申请
    METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT 有权
    制造集成电路的方法

    公开(公告)号：US20100136764A1

    公开(公告)日：2010-06-03

    申请号：US12624442

    申请日：2009-11-24

    申请人： Christoph Dirnecker ,  Philipp Steinmann ,  Badih El-Kareh

    发明人： Christoph Dirnecker ,  Philipp Steinmann ,  Badih El-Kareh

    IPC分类号： H01L21/02

    CPC分类号： H01L21/76843 ,  H01L21/76838 ,  H01L23/5228 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of manufacturing an integrated circuit comprises depositing a electrically resistive layer of a material for serving as a thin film resistor (TFR), depositing an electrically insulating layer on the resistor layer, removing the electrically insulating layer from outside an electrically active area of the resistor layer corresponding to a target TFR area, and depositing an electrically conductive layer of an electrically conductive material such that the conductive layer overlaps the target TFR area and the conductive layer electrically contacts the resistor layer outside the target TFR area.

    摘要翻译： 一种制造集成电路的方法包括沉积用作薄膜电阻器（TFR）的材料的电阻层，在电阻层上沉积电绝缘层，从电离层的电活性区域外部去除电绝缘层 对应于目标TFR区域的电阻层，以及沉积导电材料的导电层，使得导电层与靶TFR区域重叠，导电层与目标TFR区域外的电阻层电接触。

    Incubator Apparatus and Method
    25.
    发明申请
    Incubator Apparatus and Method 有权
    孵化器装置及方法

    公开(公告)号：US20090011495A1

    公开(公告)日：2009-01-08

    申请号：US12224259

    申请日：2007-02-28

    申请人： Philipp Steinmann ,  Gabriela Juarez Martinez

    发明人： Philipp Steinmann ,  Gabriela Juarez Martinez

    IPC分类号： C12M1/02 ,  B01J19/00 ,  B01L9/00 ,  C12M1/00

    CPC分类号： B01L3/50851 ,  B01L3/06 ,  B01L7/52 ,  B01L7/54 ,  B01L9/523 ,  B01L2200/147 ,  B01L2300/023 ,  B01L2300/024 ,  B01L2300/0829 ,  B01L2300/1822

    摘要： The present invention relates to a method of processing analyte using a portable incubator apparatus. The incubator apparatus 10 has a plurality of cavities 20 each configured to receive analyte to be incubated. The method comprises: receiving analyte in each of the plurality of cavities; incubating the analyte in the plurality of cavities, the incubator apparatus being operable to control temperatures of analyte contained in the plurality of cavities independently of each other; and moving the incubator apparatus from a first location to a second location whilst the analyte is being incubated, the incubator apparatus being configured to maintain desired incubation conditions independently of a supply of electrical power and apparatus external to the incubator apparatus as the incubator apparatus is being moved.

    摘要翻译： 本发明涉及使用便携式培养箱装置处理分析物的方法。 培养箱装置10具有多个空腔20，每个空腔被配置成接收要孵育的分析物。 该方法包括：在多个空腔中的每一个中接收分析物; 孵育多个空腔中的分析物，培养器装置可操作以独立地控制多个腔中包含的分析物的温度; 以及当所述分析物被孵育时，将所述培养器装置从第一位置移动到第二位置，所述培养器装置被配置为在所述培养箱装置正在进行时保持期望的温育条件，而不依赖于所述培养箱装置外部的电力供应和装置供应 移动了

    Thin film resistor head structure and method for reducing head resistivity variance
    27.
    发明授权
    Thin film resistor head structure and method for reducing head resistivity variance 有权
    薄膜电阻头结构和降低磁头电阻率方差的方法

    公开(公告)号：US07208388B2

    公开(公告)日：2007-04-24

    申请号：US11102100

    申请日：2005-04-08

    申请人： Eric W. Beach ,  Philipp Steinmann

    发明人： Eric W. Beach ,  Philipp Steinmann

    IPC分类号： H01L21/20

    CPC分类号： H01C7/006 ,  H01C17/075 ,  H01L23/5228 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of making integrated circuit thin film resistor includes forming a first dielectric layer (18B) over a substrate and providing a structure to reduce variation of head resistivity thereof by forming a dummy fill layer (9A) on the first dielectric layer, and forming a second dielectric layer (18D) over the first dummy fill layer. A thin film resistor (2) is formed on the second dielectric layer (18D). A first inter-level dielectric layer (21A) is formed on the thin film resistor and the second dielectric layer. A first metal layer (22A) is formed on the first inter-level dielectric layer and electrically contacts a portion of the thin film resistor. Preferably, the first dummy fill layer is formed as a repetitive pattern of sections such that the repetitive pattern is symmetrically aligned with respect to multiple edges of the thin-film resistor (2). Preferably, the first dummy fill layer is formed so as to extend sufficiently far beyond ends of the thin-film resistor to ensure only a negligible amount of systematic resistance error due to misalignment.

    摘要翻译： 制造集成电路薄膜电阻器的方法包括在衬底上形成第一电介质层（18B），并通过在第一电介质层上形成虚拟填充层（9A）提供减小其电阻率的变化的结构，以及 在第一虚拟填充层上形成第二介电层（18 D）。 在第二电介质层（18D）上形成薄膜电阻（2）。 第一层间电介质层（21A）形成在薄膜电阻器和第二电介质层上。 第一金属层（22A）形成在第一层间电介质层上并与薄膜电阻器的一部分电接触。 优选地，第一虚拟填充层形成为部分的重复图案，使得重复图案相对于薄膜电阻器（2）的多个边缘对称地排列。 优选地，第一虚拟填充层形成为足够远地超过薄膜电阻器的端部，以确保仅由于未对准而产生的可忽略的系统电阻误差量。