公开(公告)号：US07095073B2

公开(公告)日：2006-08-22

申请号：US10972551

申请日：2004-10-25

申请人： Subramanian Balakumar ,  Chew Hoe Ang ,  Jia Zhen Zheng ,  Paul Proctor

发明人： Subramanian Balakumar ,  Chew Hoe Ang ,  Jia Zhen Zheng ,  Paul Proctor

IPC分类号： H01L29/76

CPC分类号： H01L28/56 ,  H01L21/3141 ,  H01L21/3142 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L28/90

摘要： An improved and new process of fabricating high dielectric constant MIM capacitors. These high dielectric constant MIM capacitor met all of the stringent requirements needed for both for both RF and analog circuit applications. For the high dielectric constant MIM capacitor, the metal is comprised of copper electrodes in a dual damascene process. The dielectric constant versus the total thickness of super lattices is controlled by the number of layers either 4/4, 2/2, and 1/1 artificial layers. Hence thickness of the film can be easily controlled. Enhancement of dielectric constant is because of interface. Dielectric constants near 900 can be easily achieved for 250 Angstrom thick super lattices. MBE, molecular beam epitaxy or ALCVD, atomic layer CVD techniques is used for this type layer growth process.

摘要翻译： 一种制造高介电常数MIM电容器的改进和新工艺。 这些高介电常数MIM电容器满足RF和模拟电路应用两者所需的所有严格要求。 对于高介电常数MIM电容器，金属在双镶嵌工艺中由铜电极组成。 超级晶格的介电常数与总体厚度的关系由4/4，2/2和1/1人造层的层数控制。 因此，可以容易地控制膜的厚度。 介电常数的增强是由于界面。 接近900的介电常数可以很容易地达到250埃厚的超晶格。 MBE，分子束外延或ALCVD，原子层CVD技术用于这种类型的层生长过程。

公开(公告)号：US06897111B2

公开(公告)日：2005-05-24

申请号：US10629041

申请日：2003-07-28

申请人： Elgin Quek ,  Jia Zhen Zheng ,  Pradeep R. Yelehanka ,  Weining Li

发明人： Elgin Quek ,  Jia Zhen Zheng ,  Pradeep R. Yelehanka ,  Weining Li

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0657 ,  H01L29/66378 ,  H01L29/66393 ,  H01L29/66795

摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a horizontal semiconductor fin on top of the semiconductor substrate. An access transistor gate and a thyristor gate are then formed on top of the semiconductor substrate and in contact with the horizontal semiconductor fin. An access transistor is formed from at least a portion of the horizontal semiconductor fin and the access transistor gate. A thyristor is formed from at least a portion of the horizontal semiconductor fin and the thyristor gate, the access transistor being in contact with the thyristor.

摘要翻译： 一种用于制造集成电路结构的方法包括：在半导体衬底的顶部上提供半导体衬底和形成水平半导体鳍片。 然后在半导体衬底的顶部上形成存取晶体管栅极和晶闸管栅极，并与水平半导体鳍片接触。 存取晶体管由水平半导体鳍片和存取晶体管栅极的至少一部分形成。 晶闸管由水平半导体鳍片和晶闸管栅极的至少一部分形成，存取晶体管与晶闸管接触。

公开(公告)号：US06869884B2

公开(公告)日：2005-03-22

申请号：US10225828

申请日：2002-08-22

申请人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

发明人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/302 ,  H01L21/461 ,  H01L21/764

CPC分类号： H01L21/764 ,  H01L21/26506

摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+ or O2+ are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.

摘要翻译： 降低半导体器件衬底效应的第一种方法包括以下步骤。 O +或O 2 +被选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。 在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。 在所述至少一个上介电层上形成钝化层。 图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。 选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。 减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

公开(公告)号：US06861317B1

公开(公告)日：2005-03-01

申请号：US10664211

申请日：2003-09-17

申请人： Purakh Raj Verma ,  Sanford Chu ,  Lap Chan ,  Yelehanka Pradeep ,  Kai Shao ,  Jia Zhen Zheng

发明人： Purakh Raj Verma ,  Sanford Chu ,  Lap Chan ,  Yelehanka Pradeep ,  Kai Shao ,  Jia Zhen Zheng

IPC分类号： H01L21/00 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/84 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/76802 ,  H01L21/76829

摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (fmax), and reduced gate delay.

摘要翻译： 描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。 传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。 沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。 然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。 然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。 在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。 具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作时的噪声性能，增加的单位功率增益频率（fmax）和减小的栅极延迟。

公开(公告)号：US06780691B2

公开(公告)日：2004-08-24

申请号：US10222410

申请日：2002-08-16

申请人： Randall Cher Liang Cha ,  Yeow Kheng Lim ,  Alex Kai Hung See ,  Jia Zhen Zheng

发明人： Randall Cher Liang Cha ,  Yeow Kheng Lim ,  Alex Kai Hung See ,  Jia Zhen Zheng

IPC分类号： H01L2100

CPC分类号： H01L29/66583 ,  H01L21/28123 ,  H01L21/76235 ,  H01L21/823814 ,  H01L29/41783 ,  H01L29/665

摘要： A method for forming a transistor having an elevated source/drain structure is described. A gate electrode is formed overlying a substrate and isolated from the substrate by a gate dielectric layer. Isolation regions are formed in and on the substrate wherein the isolation regions have a stepped profile wherein an upper portion of the isolation regions partly overlaps and is offset from a lower portion of the isolation regions in the direction away from the gate electrode. Ions are implanted into the substrate between the gate electrode and the isolation regions to form source/drain extensions. Dielectric spacers are formed on sidewalls of the gate electrode and the isolation regions. A conductive layer is deposited overlying the substrate, the gate electrode, and the isolation regions and planarized to leave the conductive layer adjacent to the gate electrode and separated from the gate electrode by the dielectric spacers wherein the conductive layer forms elevated source/drain junctions and wherein the elevated source/drain junctions completely overlie the source/drain extensions and wherein an upper portion of the elevated source/drain junctions extends into the stepped portion of the isolation regions thereby completing formation of a MOSFET having an elevated source/drain structure.

公开(公告)号：US06747314B2

公开(公告)日：2004-06-08

申请号：US10242483

申请日：2002-09-12

申请人： Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek

发明人： Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek

IPC分类号： H01L2976

CPC分类号： H01L21/84 ,  H01L21/823885 ,  H01L27/1203

摘要： A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprise silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain. A gate trench is etched through the NMOS and PMOS sources and channel regions. The gate trench terminates at the NMOS and PMOS drains and exposes the sidewalls of the NMOS and PMOS channel regions. A gate oxide layer is formed overlying the NMOS and PMOS channel regions and lining the gate trench. A polysilicon layer is deposited and etched back to form polysilicon sidewalls and to thereby form gates for the closely-spaced, vertical NMOS and PMOS transistor pair.

摘要翻译： 实现了在集成电路器件中形成紧密间隔的垂直NMOS和PMOS晶体管对的方法。 衬底包括硅注入氧化物（SIMOX），其中氧化物层夹在下层和上层的硅层之间。 离子选择性地注入到上覆硅层的第一部分中以形成用于NMOS晶体管的漏极，沟道区和源极。 漏极直接形成在氧化层的上方，沟道区形成在漏极上方，源极形成在沟道区域的上方。 离子选择性地注入到上层硅层的第二部分中以形成用于PMOS晶体管的漏极，沟道区和源极。 漏极直接形成在氧化层的上方，PMOS沟道区形成在漏极上方，源极形成在沟道区域的上方。 PMOS晶体管漏极与所述NMOS晶体管漏极接触。 通过NMOS和PMOS源极和沟道区域蚀刻栅极沟槽。 栅极沟槽在NMOS和PMOS漏极处终止并暴露NMOS和PMOS沟道区的侧壁。 形成栅极氧化层，覆盖NMOS沟道区和PMOS沟道区，并衬在栅极沟槽。 沉积多晶硅层并回蚀刻以形成多晶硅侧壁，从而形成用于紧密间隔的垂直NMOS和PMOS晶体管对的栅极。

公开(公告)号：US06743291B2

公开(公告)日：2004-06-01

申请号：US10191850

申请日：2002-07-09

申请人： Chew Hoe Ang ,  Wenhe Lin ,  Jia Zhen Zheng

发明人： Chew Hoe Ang ,  Wenhe Lin ,  Jia Zhen Zheng

IPC分类号： C30B2522

CPC分类号： C30B29/06 ,  C30B25/20

摘要： A process of fabricating a CMOS device comprised with super-steep retrograde (SSR), twin well regions, has been developed. The process features the use of two, selective epitaxial growth (SEG), procedures, with the first SEG procedure resulting in the growth of bottom silicon shapes in the PMOS, as well as in the NMOS region of the CMOS device. After implantation of the ions needed for the twin well regions, into the bottom silicon shapes, a second SEG procedure is employed resulting in growth of top silicon shapes on the underlying, implanted bottom silicon shapes. An anneal procedure then distributes the implanted ions resulting in an SSR N well region in the composite silicon shape located in the PMOS region, and resulting in an SSR P well region in the composite silicon shape located in the NMOS region of the CMOS device.

摘要翻译： 已经开发了制造具有超陡逆行（SSR）双阱区的CMOS器件的工艺。 该方法的特征在于采用两种选择性外延生长（SEG）方法，其中第一种SEG方法导致PMOS中的底部硅形状以及CMOS器件的NMOS区域的生长。 在将双阱区域所需的离子植入底部硅形状之后，采用第二种SEG方法，导致底层硅底部形状的顶部硅形状的增长。 退火程序然后分布注入的离子，得到位于PMOS区域的复合硅形状中的SSR N阱区，并且导致位于CMOS器件的NMOS区域中的复合硅形状中的SSR P阱区。

公开(公告)号：US06734082B2

公开(公告)日：2004-05-11

申请号：US10213173

申请日：2002-08-06

申请人： Jia Zhen Zheng ,  Soh Yun Siah ,  Chew Hoe Ang

发明人： Jia Zhen Zheng ,  Soh Yun Siah ,  Chew Hoe Ang

IPC分类号： H01L2146

CPC分类号： H01L21/76232

摘要： A process for forming a shallow trench isolation (STI), structure in a semiconductor substrate, featuring a group of insulator liner layers located on the surfaces of the shallow trench shape used to accommodate the STI structure, has been developed. After defining a shallow trench shape featuring rounded corners, a group of thin insulator liner layers, each comprised of either silicon oxide or silicon nitride, is deposited on the exposed surfaces of the shallow trench shape via atomic layer depositing (ALD), procedures. A high density plasma procedure is used for deposition of silicon oxide, filling the shallow trench shape which is lined with the group of thin insulator liner layers. The silicon nitride component of the insulator liner layers, prevents diffusion or segregation of P type dopants from an adjacent P well region to the silicon oxide of the STI structure.

摘要翻译： 已经开发了用于形成半导体衬底中的浅沟槽隔离（STI）结构的方法，其特征在于位于用于容纳STI结构的浅沟槽形状的表面上的一组绝缘体衬垫层。 在定义了具有圆角的浅沟槽形状之后，通过原子层沉积（ALD）方法将沉积在浅沟槽形状的暴露表面上的一组薄的绝缘体衬垫层（每个都由氧化硅或氮化硅组成）沉积在一起。 使用高密度等离子体方法沉积氧化硅，填充衬有薄绝缘体衬层层的浅沟槽形状。 绝缘体衬垫层的氮化硅组分防止P型掺杂剂从相邻P阱区扩散或分离到STI结构的氧化硅上。

公开(公告)号：US06417056B1

公开(公告)日：2002-07-09

申请号：US09981439

申请日：2001-10-18

申请人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

发明人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

IPC分类号： H01L21336

CPC分类号： H01L29/66636 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7834

摘要： A method for forming a transistor having low overlap capacitance by forming a microtrench at the gate edge to reduce effective dielectric constant is described. A gate electrode is provided overlying a gate dielectric layer on a substrate and having a hard mask layer thereover. An oxide layer is formed overlying the substrate. First spacers are formed on sidewalls of the gate electrode and overlying the oxide layer. Source/drain extensions are implanted. Second spacers are formed on the first spacers. Source/drain regions are implanted. A dielectric layer is deposited overlying the gate electrode and the oxide layer and planarized to the hard mask layer whereby the first and second spacers are exposed. The exposed second spacers and underlying oxide layer are removed. The exposed substrate underlying the second spacers is etched into to form a microtrench undercutting the gate oxide layer at an edge of the gate electrode. The microtrench is filled with an epitaxial oxide layer and planarized to the hard mask layer. The dielectric layer is patterned to form third spacers on the epitaxial oxide layer. The microtrench reduces the effective dielectric constant at the overlap between the gate and the source/drain extensions to complete formation of a transistor having low overlap capacitance.

摘要翻译： 描述了通过在栅极边缘处形成微通孔以形成具有低重叠电容的晶体管以降低有效介电常数的方法。 栅电极被设置在衬底上的栅介电层上，并且在其上具有硬掩模层。 在衬底上形成氧化物层。 第一间隔物形成在栅电极的侧壁上并覆盖氧化物层。 源/漏扩展被植入。 第二间隔件形成在第一间隔件上。 源极/漏极区域被植入。 沉积覆盖在栅电极和氧化物层上的介电层，并且平坦化到硬掩模层，由此使第一和第二间隔物暴露。 去除暴露的第二间隔物和下面的氧化物层。 蚀刻第二间隔物下面的暴露的基底以形成在栅电极的边缘处切割栅极氧化物层的微切口。 微通孔填充有外延氧化物层并且平坦化到硬掩模层。 图案化电介质层以在外延氧化物层上形成第三间隔物。 微通道减小栅极和源极/漏极延伸部之间的重叠处的有效介电常数，以完成具有低重叠电容的晶体管的形成。

公开(公告)号：US06406945B1

公开(公告)日：2002-06-18

申请号：US09769810

申请日：2001-01-26

申请人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

发明人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

IPC分类号： H01L21335

CPC分类号： H01L29/517 ,  H01L21/28167 ,  H01L21/28194 ,  H01L29/42376 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66583 ,  Y10S257/90

摘要： A method for forming a gate dielectric having regions with different dielectric constants. A dummy dielectric layer is formed over a semiconductor structure. The dummy dielectric layer is patterned to form a gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the gate opening. A low-K dielectric layer is formed on the high-K dielectric layer. Spacers are formed on the low-K dielectric layer at the edges of the gate opening. The low-K dielectric layer is removed from the bottom of the gate opening between the spacers. The spacers are removed to form a stepped gate opening. The stepped gate opening has both a high-K dielectric layer and a low-K dielectric layer on the sidewalls and at the edges of the bottom of the gate opening and only a high-k dielectric layer in the center of the bottom of the stepped gate opening. A gate electrode is formed in the stepped gate opening.

摘要翻译： 一种形成具有不同介电常数区域的栅极电介质的方法。 在半导体结构上形成虚拟电介质层。 图案化虚拟介质层以形成栅极开口。 在虚拟电介质上和栅极开口中形成高K电介质层。 在高K电介质层上形成低K电介质层。 在栅极开口边缘的低K电介质层上形成间隔物。 低K电介质层从间隔物之间​​的栅极开口的底部去除。 移除间隔件以形成阶梯式门开口。 阶梯式门开口在侧壁和栅极开口底部的边缘处具有高K电介质层和低K电介质层，并且仅在台阶底部中心的高k电介质层 开门 在阶梯式门开口形成栅电极。