公开(公告)号：US09361228B2

公开(公告)日：2016-06-07

申请号：US14451639

申请日：2014-08-05

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  George Patsilaras ,  Bohuslav Rychlik

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F12/0802 ,  G06F12/0886 ,  G06F2212/1021 ,  G06F2212/401 ,  G06F2212/45 ,  G06F2212/608

Abstract: Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying, by a processor of the computing device, a base address (e.g., a physical or virtual cache address) for a first data segment, identifying a data size (e.g., based on a compression ratio) for the first data segment, obtaining a base offset based on the identified data size and the base address of the first data segment, and calculating an offset address by offsetting the base address with the obtained base offset, wherein the calculated offset address is associated with a second data segment. In some aspects, the method may include identifying a parity value for the first data segment based on the base address and obtaining the base offset by performing a lookup on a stored table using the identified data size and identified parity value.

Abstract translation: 用于在高速缓存的高速缓存行中压缩数据的方法，设备和非暂态过程可读存储介质。 方面方法可以包括由计算设备的处理器识别用于第一数据段的基地址（例如，物理或虚拟高速缓存地址），识别第一数据段的数据大小（例如，基于压缩比） 数据段，基于所识别的数据大小和第一数据段的基址获得基本偏移，并且通过利用所获得的基本偏移量偏移基址来计算偏移地址，其中所计算的偏移地址与第二数据相关联 分割。 在一些方面，所述方法可以包括基于所述基地址识别所述第一数据段的奇偶校验值，并通过使用所识别的数据大小和所识别的奇偶校验值对存储的表执行查找来获得所述基本偏移。

公开(公告)号：US20160077973A1

公开(公告)日：2016-03-17

申请号：US14483902

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： George PATSILARAS ,  Andrew Edmund Turner ,  Bohuslav Rychlik

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/0846 ,  G06F12/0851 ,  G06F12/0886 ,  G06F2212/1044 ,  G06F2212/401

Abstract: Aspects include computing devices, systems, and methods for implementing a cache memory access requests for compressed data using cache bank spreading. In an aspect, cache bank spreading may include determining whether the compressed data of the cache memory access fits on a single cache bank. In response to determining that the compressed data fits on a single cache bank, a cache bank spreading value may be calculated to replace/reinstate bank selection bits of the physical address for a cache memory of the cache memory access request that may be cleared during data compression. A cache bank spreading address in the physical space of the cache memory may include the physical address of the cache memory access request plus the reinstated bank selection bits. The cache bank spreading address may be used to read compressed data from or write compressed data to the cache memory device.

Abstract translation: 方面包括计算设备，系统和方法，用于使用高速缓存存储体扩展来实现用于压缩数据的高速缓存存储器访问请求。 在一方面，高速缓存存储体扩展可以包括确定高速缓冲存储器访问的压缩数据是否适合于单个高速缓存存储体。 响应于确定压缩数据适合于单个高速缓存存储体，可以计算高速缓存存储体扩展值以代替/恢复可以在数据期间清除的高速缓冲存储器访问请求的高速缓冲存储器的物理地址的存储体选择位 压缩。 高速缓冲存储器的物理空间中的高速缓存存储体扩展地址可以包括高速缓冲存储器访问请求的物理地址加上恢复的存储体选择位。 缓存存储体扩展地址可用于从压缩数据读取压缩数据或将压缩数据写入缓存存储器件。

公开(公告)号：US11599468B1

公开(公告)日：2023-03-07

申请号：US17538365

申请日：2021-11-30

Applicant: QUALCOMM INCORPORATED

Inventor： Andrew Edmund Turner ,  George Patsilaras

IPC: G06F12/08 ,  G06F12/084 ,  G06F12/0813 ,  G06F12/0831

Abstract: Memory system features may promote cache coherency where first and second memory clients may attempt to work on the same data. A second client cache system may provide a read request for data and associated metadata. The metadata element may be detected in a first client cache system. The first client cache system may write or flush, such as to a system memory, one or more cache lines containing the metadata and associated data and invalidate the flushed cache lines. The second client cache system may receive the data and metadata, such as from the system memory, completing or fulfilling the read request.

公开(公告)号：US20200250097A1

公开(公告)日：2020-08-06

申请号：US16269440

申请日：2019-02-06

Applicant: QUALCOMM INCORPORATED

Inventor： WESLEY JAMES HOLLAND ,  Bohuslav Rychlik ,  Andrew Edmund Turner ,  George Patsilaras ,  Jeffrey Shabel ,  Simon Peter William Booth

IPC: G06F12/0862 ,  G06F12/1009 ,  G06T1/60

Abstract: An intelligent tile-based prefetching solution executed by a compression address aperture services linearly addressed data requests from a processor to memory stored in a memory component having a tile-based address structure. The aperture monitors tile reads and seeks to match the tile read pattern to a predefined pattern. If a match is determined, the aperture executes a prefetching algorithm uniquely and optimally associated with the predefined tile read pattern. In this way, tile overfetch is mitigated while the latency on first line data reads is reduced.

公开(公告)号：US20180081817A1

公开(公告)日：2018-03-22

申请号：US15268895

申请日：2016-09-19

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner

IPC: G06F12/0888 ,  G06F12/0815

CPC classification number: G06F12/0888 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0891 ,  G06F2212/1024 ,  G06F2212/62 ,  G06F2212/621

Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing asynchronous cache maintenance operations on a computing device, including activating a first asynchronous cache maintenance operation, determining whether an active address of a memory access request to a cache is in a first range of addresses of the first active asynchronous cache maintenance operation, and queuing the first active asynchronous cache maintenance operation as the first asynchronous cache maintenance operation in a fixup queue in response to determining that the active address is in the first range of addresses.

公开(公告)号：US20180081809A1

公开(公告)日：2018-03-22

申请号：US15268791

申请日：2016-09-19

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  Bohuslav Rychlik

IPC: G06F12/0817 ,  G06F3/06 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F12/0828 ,  G06F3/0613 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0685 ,  G06F12/0835 ,  G06F13/1663 ,  G06F13/4022 ,  G06F2212/621 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing a hybrid input/output (I/O) coherent write request on a computing device, including receiving an I/O coherent write request, generating a first hybrid I/O coherent write request and a second hybrid I/O coherent write request from the I/O coherent write request, sending the first hybrid I/O coherent write request and I/O coherent write data of the I/O coherent write request to a shared memory, and sending the second hybrid I/O coherent write request without the I/O coherent write data of the I/O coherent write request to a coherency domain.

公开(公告)号：US09612971B2

公开(公告)日：2017-04-04

申请号：US14462763

申请日：2014-08-19

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  George Patsilaras ,  Bohuslav Rychlik

IPC: G06F12/00 ,  G06F12/0893 ,  G06F12/0866 ,  G06F12/0886 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0893 ,  G06F12/0866 ,  G06F12/0886 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/401 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing a cache memory access requests for data smaller than a cache line and eliminating overfetching from a main memory by writing supplemental data to the unfilled portions of the cache line. A cache memory controller may receive a cache memory access request with a supplemental write command for data smaller than a cache line. The cache memory controller may write supplemental to the portions of the cache line not filled by the data in response to a write cache memory access request or a cache miss during a read cache memory access request. In the event of a cache miss, the cache memory controller may retrieve the data from the main memory, excluding any overfetch data, and write the data and the supplemental data to the cache line. Eliminating overfetching reduces bandwidth and power required to retrieved data from main memory.

公开(公告)号：US20160203084A1

公开(公告)日：2016-07-14

申请号：US15077534

申请日：2016-03-22

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  George Patsilaras ,  Bohuslav Rychlik

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F12/0802 ,  G06F12/0886 ,  G06F2212/1021 ,  G06F2212/401 ,  G06F2212/45 ,  G06F2212/608

Abstract: Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying, by a processor of the computing device, a base address (e.g., a physical or virtual cache address) for a first data segment, identifying a data size (e.g., based on a compression ratio) for the first data segment, obtaining a base offset based on the identified data size and the base address of the first data segment, and calculating an offset address by offsetting the base address with the obtained base offset, wherein the calculated offset address is associated with a second data segment. In some aspects, the method may include identifying a parity value for the first data segment based on the base address and obtaining the base offset by performing a lookup on a stored table using the identified data size and identified parity value.

Abstract translation: 用于在高速缓存的高速缓存行中压缩数据的方法，设备和非暂态过程可读存储介质。 方面方法可以包括由计算设备的处理器识别用于第一数据段的基地址（例如，物理或虚拟高速缓存地址），识别第一数据段的数据大小（例如，基于压缩比） 数据段，基于所识别的数据大小和第一数据段的基址获得基本偏移，并且通过利用所获得的基本偏移量偏移基址来计算偏移地址，其中所计算的偏移地址与第二数据相关联 分割。 在一些方面，所述方法可以包括基于所述基地址识别所述第一数据段的奇偶校验值，并通过使用所识别的数据大小和所识别的奇偶校验值对存储的表执行查找来获得所述基本偏移。

公开(公告)号：US09355038B2

公开(公告)日：2016-05-31

申请号：US14483902

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： George Patsilaras ,  Andrew Edmund Turner ,  Bohuslav Rychlik

IPC: G06F12/06 ,  G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/0846 ,  G06F12/0851 ,  G06F12/0886 ,  G06F2212/1044 ,  G06F2212/401

Abstract: Aspects include computing devices, systems, and methods for implementing a cache memory access requests for compressed data using cache bank spreading. In an aspect, cache bank spreading may include determining whether the compressed data of the cache memory access fits on a single cache bank. In response to determining that the compressed data fits on a single cache bank, a cache bank spreading value may be calculated to replace/reinstate bank selection bits of the physical address for a cache memory of the cache memory access request that may be cleared during data compression. A cache bank spreading address in the physical space of the cache memory may include the physical address of the cache memory access request plus the reinstated bank selection bits. The cache bank spreading address may be used to read compressed data from or write compressed data to the cache memory device.

Abstract translation: 方面包括计算设备，系统和方法，用于使用高速缓存存储体扩展来实现用于压缩数据的高速缓存存储器访问请求。 在一方面，高速缓存存储体扩展可以包括确定高速缓冲存储器访问的压缩数据是否适合于单个高速缓存存储体。 响应于确定压缩数据适合于单个高速缓存存储体，可以计算高速缓存存储体扩展值以代替/恢复可以在数据期间清除的高速缓冲存储器访问请求的高速缓冲存储器的物理地址的存储体选择位 压缩。 高速缓冲存储器的物理空间中的高速缓存存储体扩展地址可以包括高速缓冲存储器访问请求的物理地址加上恢复的存储体选择位。 缓存存储体扩展地址可用于从压缩数据读取压缩数据或将压缩数据写入缓存存储器件。

公开(公告)号：US20160055094A1

公开(公告)日：2016-02-25

申请号：US14462773

申请日：2014-08-19

Applicant: QUALCOMM Incorporated

Inventor： George Patsilaras ,  Ali Iranli ,  Andrew Edmund Turner ,  Bohuslav Rychlik

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/0886 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/401 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing a cache memory access requests for data smaller than a cache line and eliminating overfetching from a main memory by combining the data with padding data of a size of a difference between a size of a cache line and the data. A processor may determine whether the data, uncompressed or compressed, is smaller than a cache line using a size of the data or a compression ratio of the data. The processor may generate the padding data using constant data values or a pattern of data values. The processor may send a write cache memory access request for the combined data to a cache memory controller, which may write the combined data to a cache memory. The cache memory controller may send a write memory access request to a memory controller, which may write the combined data to a memory.

Abstract translation: 方面包括计算设备，系统和方法，用于对小于高速缓存线的数据实现高速缓冲存储器访问请求，并且通过将数据与高速缓存行的大小之间的差大小的填充数据组合来消除从主存储器的超时 和数据。 处理器可以使用数据的大小或数据的压缩比来确定未压缩或压缩的数据是否小于高速缓存行。 处理器可以使用恒定的数据值或数据值的模式来生成填充数据。 处理器可以将组合数据的写高速缓存存储器访问请求发送到高速缓冲存储器控制器，高速缓冲存储器控制器可以将组合的数据写入高速缓冲存储器。 高速缓冲存储器控制器可以将写存储器访问请求发送到存储器控制器，存储器控制器可以将组合的数据写入存储器。