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    TECHNIQUES FOR THERMAL MATCHING OF INTEGRATED CIRCUITS
    21.
    发明申请
    TECHNIQUES FOR THERMAL MATCHING OF INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20200312786A1

    公开(公告)日：2020-10-01

    申请号：US16362951

    申请日：2019-03-25

    Applicant: QUALCOMM Incorporated

    Inventor： Bin YANG ,  Kai LIU ,  Xia LI

    IPC: H01L23/00 ,  H01L25/16 ,  H01L23/498

    Abstract: Certain aspects of the present disclosure provide apparatus for thermal matching of integrated circuits (ICs). One example apparatus generally includes a first substrate, a first IC disposed on the first substrate and having a second substrate, and a second IC disposed on the first substrate. The second IC may include a third substrate, a thermal conductivity adjustment region comprising different material than the third substrate, the thermal conductivity adjustment region being adjacent to a first side of the third substrate, and one or more electrical components formed in one or more layers of the second IC adjacent to a second side of the third substrate, wherein the first side and the second side are opposite sides of the third substrate, and wherein a thermal conductivity of the thermal conductivity adjustment region is closer to a thermal conductivity of the second substrate than a thermal conductivity of the third substrate.

    COUPLED INDUCTORS THROUGH SUBSTRATE-ASSEMBLY PROCESS AND/OR WAFER-LEVEL PROCESS
    24.
    发明公开
    COUPLED INDUCTORS THROUGH SUBSTRATE-ASSEMBLY PROCESS AND/OR WAFER-LEVEL PROCESS 审中-公开

    公开(公告)号：US20240304545A1

    公开(公告)日：2024-09-12

    申请号：US18182080

    申请日：2023-03-10

    Applicant: QUALCOMM Incorporated

    Inventor： Kai LIU ,  Nosun PARK ,  Jonghae KIM

    IPC: H01L23/522 ,  H01L23/538

    CPC classification number: H01L23/5227 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5386 ,  H01L28/10

    Abstract: Compact coupled inductor designs are disclosed. In an aspect, a coupled inductor comprises a pair of inductors, each inductor comprising an alternating series of metallization structures and wire bonds forming a spiral topology around a common central axis, wherein the pair of inductors are interleaved with each other along the common central axis, such that at least some of the metallization structures of one of the pair of inductors are electrically coupled with at least some of the metallization structures of the other of the pair of inductors, and at least some of the wire bonds of one of the pair of inductors are electrically coupled with at least some of the wire bonds of the other of the pair of inductors. The shapes of the wire bonds can be selected to produce a desired coupling coefficient.

    THREE-DIMENSIONAL VERTICAL CO-SPIRAL INDUCTORS
    26.
    发明公开
    THREE-DIMENSIONAL VERTICAL CO-SPIRAL INDUCTORS 审中-公开

    公开(公告)号：US20240021353A1

    公开(公告)日：2024-01-18

    申请号：US17812772

    申请日：2022-07-15

    Applicant: QUALCOMM Incorporated

    Inventor： Jonghae KIM ,  Je-Hsiung LAN ,  Kai LIU ,  Ranadeep DUTTA

    IPC: H01F17/00 ,  H01F27/28

    CPC classification number: H01F17/0013 ,  H01F27/2804 ,  H01F2027/2809

    Abstract: One or more aspects include apparatuses, systems including co-spiral inductors and methods for fabricating the same. In at least one aspect, a co-spiral inductor includes a plurality of turns, each of the plurality of turns being displaced both vertically and horizontally from a next successive turn. The plurality of turns is formed from traces on different metal layers formed on a substrate. The co-spiral inductor includes a plurality of insulators configured to electrically insulate each of the plurality of turns. The co-spiral inductor includes a plurality of interconnects configured to couple each of the plurality of turns to at least one other turn.

    CAPACITOR EMBEDDED 3D RESONATOR FOR BROADBAND FILTER
    29.
    发明公开
    CAPACITOR EMBEDDED 3D RESONATOR FOR BROADBAND FILTER 审中-公开

    公开(公告)号：US20230275004A1

    公开(公告)日：2023-08-31

    申请号：US17682868

    申请日：2022-02-28

    Applicant: QUALCOMM Incorporated

    Inventor： Jonghae KIM ,  Je-Hsiung LAN ,  Kai LIU ,  Ranadeep DUTTA

    IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H03H7/01

    CPC classification number: H01L23/481 ,  H01L23/5223 ,  H01L21/76898 ,  H03H7/0115 ,  H01L23/5227

    Abstract: An integrated circuit (IC) includes a substrate and a first through substrate via (TSV) in the substrate. The first TSV includes a first metal-insulator-metal (MIM) capacitor. The first MIM capacitor includes a first plate composed of a first metallization layer on an inner surface of the first TSV. The first MIM capacitor includes a MIM insulator layer on the first plate. The first MIM capacitor includes a second plate composed of a second metallization layer on the MIM insulator layer. The IC includes a 3D inductor. The 3D inductor includes a second TSV in the substrate. The 3D inductor includes a first trace on a first surface of the substrate, coupled to a first end of the second TSV. The 3D inductor further includes a second trace on a second surface of the substrate and coupled to a second end of the second TSV and a second end of the first TSV.

    THERMAL PATHS FOR GLASS SUBSTRATES
    30.
    发明申请
    THERMAL PATHS FOR GLASS SUBSTRATES 有权

    公开(公告)号：US20210304944A1

    公开(公告)日：2021-09-30

    申请号：US16835227

    申请日：2020-03-30

    Applicant: QUALCOMM Incorporated

    Inventor： Kai LIU ,  Xiaoju YU ,  Xia LI ,  Bin YANG

    IPC: H01F27/22 ,  H01G4/33 ,  H01G4/252 ,  H01F27/29

    Abstract: Examples herein include thermally conductive pathways for glass substrates such as used by passive on glass devices that may be used to enhance the thermal conductivity of an integrated POG device. By using a thermally conductive material for passivation of the device pathways during manufacturing, the device pathways may be able to conduct heat away from the device. For example, by using a selected poly (p-phenylene benzobisoxazole) (PBO) based material (e.g., poly-p-phenylene-2, 6-benzobisoxazole) instead of conventional polyimide (PI) materials during a Cu pattern passivation process, the overall thermal performance of the device, may be enhanced.

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