公开(公告)号：US09515621B2

公开(公告)日：2016-12-06

申请号：US13689883

申请日：2012-11-30

Applicant: RF Micro Devices, Inc.

Inventor： Alexander Wayne Hietala ,  Jeffery Peter Ortiz ,  David Halchin ,  Jackie Johnson ,  Wendel Charles

IPC: H03F3/21 ,  H03F3/68 ,  H03F1/02 ,  H03F3/195 ,  H03F3/24 ,  H03F3/72

CPC classification number: H03F3/211 ,  H03F1/0277 ,  H03F3/195 ,  H03F3/245 ,  H03F3/72 ,  H03F2200/429 ,  H03F2200/507 ,  H03F2200/537 ,  H03F2203/21145 ,  H03F2203/7209 ,  H03F2203/7227

Abstract: Multimode radio frequency (RF) amplifier systems and techniques are disclosed. In one embodiment, a multimode radio frequency (RF) amplifier system has a first RF amplifier and a second RF amplifier. The first RF amplifier may support a first RF communication standard. The second RF amplifier may support a second RF communication standard. The first RF amplifier includes an auxiliary circuit. The auxiliary circuit may provide a service or a utility to a second RF amplifier. For example, the auxiliary circuit may generate a supply voltage to power the second RF amplifier.

Abstract translation: 公开了多模射频（RF）放大器系统和技术。 在一个实施例中，多模射频（RF）放大器系统具有第一RF放大器和第二RF放大器。 第一RF放大器可以支持第一RF通信标准。 第二RF放大器可以支持第二RF通信标准。 第一RF放大器包括辅助电路。 辅助电路可以向第二RF放大器提供服务或实用工具。 例如，辅助电路可以产生电源电压以对第二RF放大器供电。

公开(公告)号：US20160134014A1

公开(公告)日：2016-05-12

申请号：US14933552

申请日：2015-11-05

Applicant: RF Micro Devices, Inc.

Inventor： Alexander Wayne Hietala ,  Julio C. Costa

IPC: H01Q1/52 ,  H01Q3/28 ,  H01Q3/30 ,  H01Q19/10 ,  H01Q3/44

Abstract: Aspects disclosed in the detailed description include an antenna on a device assembly. A device assembly includes a silicon device layer having at least one antenna. The device assembly also includes a polymer substrate that is formed with insulating material that does not interfere with the at least one antenna in the silicon device layer. As a result, it is unnecessary to shield the at least one antenna from the polymer substrate, thus allowing radio frequency (RF) signals radiating from the at least one antenna to pass through the polymer substrate.

Abstract translation: 详细描述中公开的方面包括设备组件上的天线。 一种器件组件包括具有至少一个天线的硅器件层。 所述器件组件还包括聚合物衬底，所述聚合物衬底由不与硅器件层中的至少一个天线干涉的绝缘材料形成。 结果，不需要从聚合物基板屏蔽至少一个天线，从而允许从至少一个天线辐射的射频（RF）信号通过聚合物基板。

公开(公告)号：US20140038675A1

公开(公告)日：2014-02-06

申请号：US14051601

申请日：2013-10-11

Applicant: RF Micro Devices, Inc.

Inventor： Nadim Khlat ,  Alexander Wayne Hietala

IPC: H04W52/02

CPC classification number: H04W52/0251 ,  H03F1/02 ,  H03F1/0227 ,  H03F3/24 ,  H03F3/68 ,  H03F3/72 ,  H03F2203/7209 ,  H03F2203/7221 ,  H04B1/0067 ,  H04B2001/045 ,  H04L5/001

Abstract: A front end radio architecture (FERA) with power management is disclosed. The FERA includes a first power amplifier (PA) block having a first-first PA for amplifying first-first signals and a first-second PA for amplifying first-second signals. Also included is a second PA block having a second-first PA for amplifying second-first signals and a second-second PA for amplifying second-second signals. At least one power supply is adapted to selectively supply power to the first-first PA and the second-second PA through a first path. The power supply is also adapted to selectively supply power to the first-second PA and the second-first PA through a second path. A control system is adapted to selectively enable and disable the first-first PA, the first-second PA, the second-first PA, and the second-second PA.

Abstract translation: 公开了具有电源管理的前端无线电架构（FERA）。 FERA包括具有用于放大第一信号的第一第一PA和用于放大第一秒信号的第一秒PA的第一功率放大器（PA）模块。 还包括具有用于放大第二第一信号的第二第一PA和用于放大第二秒信号的第二秒PA的第二PA块。 至少一个电源适于通过第一路径选择性地向第一首PA和第二秒PA供电。 电源还适于通过第二路径选择性地向第一和第二PA供电。 控制系统适于选择性地启用和禁用第一优先PA，第一秒PA，第二优先PA和第二秒PA。

公开(公告)号：US10528502B2

公开(公告)日：2020-01-07

申请号：US14659371

申请日：2015-03-16

Applicant: RF Micro Devices, Inc.

Inventor： Christopher Truong Ngo ,  Alexander Wayne Hietala ,  Christian Rye Iversen ,  Ruediger Bauder

IPC: G06F13/364

Abstract: Embodiments of bus interface systems are disclosed. In one embodiment, a bus interface system includes a master bus controller and a slave bus controller coupled along a bus line. The master bus controller is configured to generate an input data signal that is received by the slave bus controller along the bus line. The slave bus controller includes power conversion circuitry configured to convert the input data signal from the master bus controller into a supply voltage. By providing the power conversion circuitry, the slave bus controller is powered using the input data signal and without requiring an additional bus line to transfer a supply voltage to the slave bus controller.

公开(公告)号：US10185683B2

公开(公告)日：2019-01-22

申请号：US14575491

申请日：2014-12-18

Applicant: RF Micro Devices, Inc.

Inventor： Christopher Truong Ngo ,  Alexander Wayne Hietala ,  Christian Rye Iversen ,  Ruediger Bauder

IPC: G06F13/00 ,  G06F13/362 ,  G06F13/42

Abstract: A bus interface system is disclosed that includes a master bus controller and a slave bus controller that are coupled by a bus line. The slave bus controller includes a decoder that allows for data to be transmitted along just the bus line. The decoder includes an oscillator, a first counter, and a comparison circuit. The oscillator is configured to be enabled by data pulses defined by the input data signal and generate oscillation pulses while enabled. The first counts the oscillation pulses and indicates a number of the oscillation pulses generated during a time slot. The comparison circuit is configured to this number with a reference number and generate a data output that represents a first logical value in response to the number being greater than the reference parameter and represents a second logical value in response to the number being less than the reference parameter.

公开(公告)号：US09220067B2

公开(公告)日：2015-12-22

申请号：US14051601

申请日：2013-10-11

Applicant: RF Micro Devices, Inc.

Inventor： Nadim Khlat ,  Alexander Wayne Hietala

IPC: H04B7/00 ,  H04W52/02 ,  H03F1/02 ,  H03F3/24 ,  H03F3/68 ,  H03F3/72 ,  H04B1/00 ,  H04L5/00 ,  H04B1/04

CPC classification number: H04W52/0251 ,  H03F1/02 ,  H03F1/0227 ,  H03F3/24 ,  H03F3/68 ,  H03F3/72 ,  H03F2203/7209 ,  H03F2203/7221 ,  H04B1/0067 ,  H04B2001/045 ,  H04L5/001

Abstract: A front end radio architecture (FERA) with power management is disclosed. The FERA includes a first power amplifier (PA) block having a first-first PA for amplifying first-first signals and a first-second PA for amplifying first-second signals. Also included is a second PA block having a second-first PA for amplifying second-first signals and a second-second PA for amplifying second-second signals. At least one power supply is adapted to selectively supply power to the first-first PA and the second-second PA through a first path. The power supply is also adapted to selectively supply power to the first-second PA and the second-first PA through a second path. A control system is adapted to selectively enable and disable the first-first PA, the first-second PA, the second-first PA, and the second-second PA.

Abstract translation: 公开了具有电源管理的前端无线电架构（FERA）。 FERA包括具有用于放大第一信号的第一第一PA和用于放大第一秒信号的第一秒PA的第一功率放大器（PA）模块。 还包括具有用于放大第二第一信号的第二第一PA和用于放大第二秒信号的第二秒PA的第二PA块。 至少一个电源适于通过第一路径选择性地向第一首PA和第二秒PA供电。 电源还适于通过第二路径选择性地向第一和第二PA供电。 控制系统适于选择性地启用和禁用第一优先PA，第一秒PA，第二优先PA和第二秒PA。

公开(公告)号：US20150193373A1

公开(公告)日：2015-07-09

申请号：US14659292

申请日：2015-03-16

Applicant: RF Micro Devices, Inc.

Inventor： Christopher Truong Ngo ,  Alexander Wayne Hietala

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/364

CPC classification number: G06F13/4291 ,  G06F13/3625 ,  G06F13/364 ,  G06F13/4018

Abstract: The disclosure relates to bus interface systems. In one embodiment, the bus interface system includes a bus line along with a master bus controller and a slave bus controller coupled to the bus line. In order to start a data frame, the master bus controller is configured to generate a sequence of data pulses along the bus line such that the sequence of data pulses is provided in accordance to a start of sequence (SOS) pulse pattern. The slave bus controller is configured to recognize that the sequence of data transmitted along the bus line by the master bus controller has been provided in accordance with the SOS pulse pattern. In this manner, the slave bus controller can detect when the master bus controller has started a new data frame. As such, the exchange of information through data frames can be synchronized along the bus line with requiring an additional bus line for a clock signal.

Abstract translation: 本公开涉及总线接口系统。 在一个实施例中，总线接口系统包括总线线路以及主总线控制器和耦合到总线线路的从总线控制器。 为了开始数据帧，主总线控制器被配置为沿着总线生成一系列数据脉冲，使得根据序列开始（SOS）脉冲模式提供数据脉冲序列。 从总线控制器被配置为识别主总线控制器沿总线发送的数据序列是根据SOS脉冲模式提供的。 以这种方式，从总线控制器可以检测主总线控制器何时开始新的数据帧。 因此，通过数据帧的信息交换可以沿着总线同步，同时需要用于时钟信号的附加总线。

公开(公告)号：US09071210B2

公开(公告)日：2015-06-30

申请号：US14056135

申请日：2013-10-17

Applicant: RF Micro Devices, Inc.

Inventor： Nadim Khlat ,  Alexander Wayne Hietala

IPC: H03F1/14 ,  H03F1/56 ,  H03F3/20 ,  H03F3/68 ,  H03F3/24

CPC classification number: H03F1/56 ,  H03F3/20 ,  H03F3/24 ,  H03F3/68 ,  H03F2200/387 ,  H03F2200/537 ,  H03F2200/541

Abstract: An efficient power transfer power amplifier (PA) architecture is disclosed that includes a first PA, a first impedance transformation network (ITN) coupled to the first PA, a second PA, and a second ITN coupled to the second PA. A switching network having a plurality of load outputs along with a first switch input coupled to a first impedance output of the first ITN and a second switch input coupled to a second impedance output of the first ITN, a third switch input coupled to a third impedance output of the second ITN, and a fourth switch input coupled to a fourth impedance output of the second ITN. A control system is adapted to control the switching network to switch signals at the first, second, third, and fourth switch inputs such that select ones of the signals travel paths having matching impedances to loads coupled to the plurality of load outputs.

Abstract translation: 公开了一种有效的功率传输功率放大器（PA）架构，其包括第一PA，耦合到第一PA的第一阻抗变换网络（ITN），第二PA和耦合到第二PA的第二ITN。 一种具有多个负载输出以及耦合到第一ITN的第一阻抗输出的第一开关输入和耦合到第一ITN的第二阻抗输出的第二开关输入的开关网络，耦合到第三阻抗的第三开关输入 第二ITN的输出和耦合到第二ITN的第四阻抗输出的第四开关输入。 控制系统适于控制开关网络以在第一，第二，第三和第四开关输入端切换信号，使得信号中的选择信号将具有匹配阻抗的路径传递到耦合到多个负载输出的负载。

公开(公告)号：US08907726B2

公开(公告)日：2014-12-09

申请号：US13668641

申请日：2012-11-05

Applicant: RF Micro Devices, Inc.

Inventor： Jeffery P. Ortiz ,  Alexander Wayne Hietala

IPC: H03F3/45 ,  H03G3/30

CPC classification number: H03G3/3042

Abstract: In one embodiment, saturation of the control system of a power amplifier is limited by comparing a control voltage at a first control node against a scaled battery voltage, and then drawing an error current away from the first control node when the control voltage exceeds the scaled battery voltage. The first control node may be located after a trans-conductance amplifier in a feedback control system.

Abstract translation: 在一个实施例中，通过将第一控制节点处的控制电压与缩放的电池电压进行比较来限制功率放大器的控制系统的饱和度，然后当控制电压超过定标的电池时，从第一控制节点引出误差电流 电池电压。 第一控制节点可以位于反馈控制系统中的跨导放大器之后。

公开(公告)号：US20140304442A1

公开(公告)日：2014-10-09

申请号：US14160900

申请日：2014-01-22

Applicant: RF Micro Devices, Inc.

Inventor： Alexander Wayne Hietala ,  Christopher Truong Ngo ,  Eric K. Bolton

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  Y02D10/14 ,  Y02D10/151

Abstract: Disclosed is a digital communication control system having a serial bus buffer that includes a primary interface adapted to support serial communication over a primary bus, a buffered interface adapted to support serial communication over a buffered bus, and a controller coupled between the primary bus and the buffered bus. The primary bus is coupled to a first device and at least one second device and the buffered bus is coupled to at least one third device. The controller is adapted to receive a first data signal and a clock signal at the primary interface and replicate the first data signal and the clock signal at the buffered interface.

Abstract translation: 公开了一种具有串行总线缓冲器的数字通信控制系统，该串行总线缓冲器包括适于支持通过主总线的串行通信的主接口，适于支持通过缓冲总线的串行通信的缓冲接口以及耦合在主总线与 缓冲总线。 主总线耦合到第一设备和至少一个第二设备，并且缓冲总线耦合到至少一个第三设备。 控制器适于在主接口处接收第一数据信号和时钟信号，并在缓冲接口处复制第一数据信号和时钟信号。