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    ANTENNA TUNING CIRCUITRY WITH REDUCED INTERFERENCE
    1.
    发明申请
    ANTENNA TUNING CIRCUITRY WITH REDUCED INTERFERENCE 有权
    天线调谐电路具有减少的干扰

    公开(公告)号：US20150054698A1

    公开(公告)日：2015-02-26

    申请号：US14465142

    申请日：2014-08-21

    Applicant: RF Micro Devices, Inc.

    Inventor： Daniel Charles Kerr ,  Christian Rye Iversen ,  Eric K. Bolton ,  Ruediger Bauder ,  Nadim Khlat

    IPC: H01Q5/00

    CPC classification number: H01Q5/328 ,  H01Q5/335

    Abstract: Antenna tuning circuitry includes an antenna tuning node, an antenna tuning switch, and a resonant tuning circuit. The antenna tuning node is coupled to a resonant conduction element of an antenna. The antenna tuning switch and the resonant tuning circuit are coupled in series between the antenna tuning switch and the antenna tuning node, such that the resonant tuning circuit is between the antenna tuning node and the antenna tuning switch. The resonant tuning circuit is configured to resonate at one or more harmonic frequencies generated by the antenna tuning switch such that a high impedance path is formed between the antenna tuning switch and the antenna tuning node at harmonic frequencies generated by the antenna tuning switch. Accordingly, harmonic interference generated by the antenna tuning switch is prevented from reaching the antenna, while simultaneously allowing for tuning of the antenna.

    Abstract translation: 天线调谐电路包括天线调谐节点，天线调谐开关和谐振调谐电路。 天线调谐节点耦合到天线的谐振传导元件。 天线调谐开关和谐振调谐电路串联在天线调谐开关和天线调谐节点之间，使得谐振调谐电路在天线调谐节点和天线调谐开关之间。 谐振调谐电路被配置为在由天线调谐开关产生的一个或多个谐波频率下谐振，使得在天线调谐开关和天线调谐节点之间以由天线调谐开关产生的谐波频率形成高阻抗路径。 因此，防止由天线调谐开关产生的谐波干扰到达天线，同时允许调谐天线。

    TECHNIQUE TO REDUCE THE THIRD HARMONIC OF AN ON-STATE RF SWITCH
    2.
    发明申请
    TECHNIQUE TO REDUCE THE THIRD HARMONIC OF AN ON-STATE RF SWITCH 有权
    降低状态RF开关的第三谐波的技术

    公开(公告)号：US20140335801A1

    公开(公告)日：2014-11-13

    申请号：US14271921

    申请日：2014-05-07

    Applicant: RF Micro Devices, Inc.

    Inventor： Eric K. Bolton ,  Daniel Charles Kerr ,  Marcus Granger-Jones

    IPC: H04B1/44

    CPC classification number: H04B15/02

    Abstract: RF switching circuitry includes an RF switch coupled between an input node and an output node. Distortion compensation circuitry is coupled in parallel with the RF switch between the input node and the output node. The RF switch is configured to selectively pass an RF signal from the input node to the output node based on a first switching control signal. The distortion compensation circuitry is configured to boost a portion of the RF signal that is being compressed by the RF switch when the amplitude of the RF signal is above a predetermined threshold by selectively injecting current into one of the input node or the output node. Boosting a portion of the RF signal that is being compressed by the RF switch allows a signal passing through the RF switch to remain substantially linear, thereby improving the performance of the RF switching circuitry.

    Abstract translation: RF切换电路包括耦合在输入节点和输出节点之间的RF开关。 失真补偿电路与输入节点和输出节点之间的RF开关并联耦合。 RF开关被配置为基于第一开关控制信号选择性地将RF信号从输入节点传递到输出节点。 失真补偿电路被配置为通过选择性地将电流注入到输入节点或输出节点之一时，通过RF信号的幅度高于预定阈值来升高被RF开关压缩的RF信号的一部分。 升高由RF开关压缩的RF信号的一部分允许通过RF开关的信号保持基本上线性，从而提高RF开关电路的性能。

    Harmonic cancellation circuit for an RF switch branch
    3.
    发明授权
    Harmonic cancellation circuit for an RF switch branch 有权
    RF开关分支的谐波消除电路

    公开(公告)号：US09240770B2

    公开(公告)日：2016-01-19

    申请号：US14212831

    申请日：2014-03-14

    Applicant: RF Micro Devices, Inc.

    Inventor： Daniel Charles Kerr ,  Eric K. Bolton ,  Robert Andrew Phelps

    IPC: H03K17/687 ,  H03H11/12 ,  H03K17/693 ,  H01P1/15 ,  H03K17/10

    CPC classification number: H03H11/1213 ,  H01P1/15 ,  H03K17/102 ,  H03K17/687 ,  H03K17/693

    Abstract: Disclosed is a harmonic cancellation circuit for an RF switch branch having a first transistor with a first gate terminal and a first body terminal, a second transistor having a second gate terminal coupled to the first body terminal, and having a second body terminal coupled to the first gate terminal. Also included is a first resistor coupled between a first coupling node and the second body terminal, and a second resistor coupled between a second coupling node and the first body terminal, wherein the first transistor and second transistor are adapted to generate an inverse phase third harmonic signal relative to a third harmonic signal generated by the RF switch branch, such that the inverse phase third harmonic signal is output through the first resistor and the second resistor to the RF switch branch to reduce the third harmonic signal.

    Abstract translation: 公开了一种用于RF开关分支的谐波消除电路，具有具有第一栅极端子和第一主体端子的第一晶体管，第二晶体管具有耦合到第一主体端子的第二栅极端子，并且具有耦合到第一主体端子的第二主体端子 第一门终端。 还包括耦合在第一耦合节点和第二主体端子之间的第一电阻器和耦合在第二耦合节点和第一主体端子之间的第二电阻器，其中第一晶体管和第二晶体管适于产生反相三次谐波 信号相对于由RF开关分支产生的三次谐波信号，使得反相三次谐波信号通过第一电阻器和第二电阻器输出到RF开关分支以减少三次谐波信号。

    Antenna tuning circuitry with reduced interference
    4.
    发明授权
    Antenna tuning circuitry with reduced interference 有权

    公开(公告)号：US09865922B2

    公开(公告)日：2018-01-09

    申请号：US14465142

    申请日：2014-08-21

    Applicant: RF Micro Devices, Inc.

    Inventor： Daniel Charles Kerr ,  Christian Rye Iversen ,  Eric K. Bolton ,  Ruediger Bauder ,  Nadim Khlat

    IPC: H01Q5/328 ,  H01Q5/335

    CPC classification number: H01Q5/328 ,  H01Q5/335

    Abstract: Antenna tuning circuitry includes an antenna tuning node, an antenna tuning switch, and a resonant tuning circuit. The antenna tuning node is coupled to a resonant conduction element of an antenna. The antenna tuning switch and the resonant tuning circuit are coupled in series between the antenna tuning switch and the antenna tuning node, such that the resonant tuning circuit is between the antenna tuning node and the antenna tuning switch. The resonant tuning circuit is configured to resonate at one or more harmonic frequencies generated by the antenna tuning switch such that a high impedance path is formed between the antenna tuning switch and the antenna tuning node at harmonic frequencies generated by the antenna tuning switch. Accordingly, harmonic interference generated by the antenna tuning switch is prevented from reaching the antenna, while simultaneously allowing for tuning of the antenna.

    Serial bus buffer with noise reduction
    5.
    发明授权
    Serial bus buffer with noise reduction 有权
    具有降噪功能的串行总线缓冲器

    公开(公告)号：US09519612B2

    公开(公告)日：2016-12-13

    申请号：US14160900

    申请日：2014-01-22

    Applicant: RF Micro Devices, Inc.

    Inventor： Alexander Wayne Hietala ,  Christopher Truong Ngo ,  Eric K. Bolton

    IPC: G06F13/24 ,  G06F13/42

    CPC classification number: G06F13/4291 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Disclosed is a digital communication control system having a serial bus buffer that includes a primary interface adapted to support serial communication over a primary bus, a buffered interface adapted to support serial communication over a buffered bus, and a controller coupled between the primary bus and the buffered bus. The primary bus is coupled to a first device and at least one second device and the buffered bus is coupled to at least one third device. The controller is adapted to receive a first data signal and a clock signal at the primary interface and replicate the first data signal and the clock signal at the buffered interface.

    Abstract translation: 公开了一种具有串行总线缓冲器的数字通信控制系统，该串行总线缓冲器包括适于支持通过主总线的串行通信的主接口，适于支持通过缓冲总线的串行通信的缓冲接口以及耦合在主总线与 缓冲总线。 主总线耦合到第一设备和至少一个第二设备，并且缓冲总线耦合到至少一个第三设备。 控制器适于在主接口处接收第一数据信号和时钟信号，并在缓冲接口处复制第一数据信号和时钟信号。

    Technique to reduce the third harmonic of an on-state RF switch
    6.
    发明授权
    Technique to reduce the third harmonic of an on-state RF switch 有权
    降低导通状态RF开关三次谐波的技术

    公开(公告)号：US09236957B2

    公开(公告)日：2016-01-12

    申请号：US14271921

    申请日：2014-05-07

    Applicant: RF Micro Devices, Inc.

    Inventor： Eric K. Bolton ,  Daniel Charles Kerr ,  Marcus Granger-Jones

    IPC: H04B1/44 ,  H04B15/02

    CPC classification number: H04B15/02

    Abstract: RF switching circuitry includes an RF switch coupled between an input node and an output node. Distortion compensation circuitry is coupled in parallel with the RF switch between the input node and the output node. The RF switch is configured to selectively pass an RF signal from the input node to the output node based on a first switching control signal. The distortion compensation circuitry is configured to boost a portion of the RF signal that is being compressed by the RF switch when the amplitude of the RF signal is above a predetermined threshold by selectively injecting current into one of the input node or the output node. Boosting a portion of the RF signal that is being compressed by the RF switch allows a signal passing through the RF switch to remain substantially linear, thereby improving the performance of the RF switching circuitry.

    Abstract translation: RF切换电路包括耦合在输入节点和输出节点之间的RF开关。 失真补偿电路与输入节点和输出节点之间的RF开关并联耦合。 RF开关被配置为基于第一开关控制信号选择性地将RF信号从输入节点传递到输出节点。 失真补偿电路被配置为通过选择性地将电流注入到输入节点或输出节点之一时，通过RF信号的幅度高于预定阈值来升高被RF开关压缩的RF信号的一部分。 升高由RF开关压缩的RF信号的一部分允许通过RF开关的信号保持基本上线性，从而提高RF开关电路的性能。

    HARMONIC CANCELLATION CIRCUIT FOR AN RF SWITCH BRANCH
    8.
    发明申请
    HARMONIC CANCELLATION CIRCUIT FOR AN RF SWITCH BRANCH 有权
    用于RF开关分支的谐波消除电路

    公开(公告)号：US20140266415A1

    公开(公告)日：2014-09-18

    申请号：US14212831

    申请日：2014-03-14

    Applicant: RF Micro Devices, Inc.

    Inventor： Daniel Charles Kerr ,  Eric K. Bolton ,  Robert Andrew Phelps

    IPC: H03H11/04

    CPC classification number: H03H11/1213 ,  H01P1/15 ,  H03K17/102 ,  H03K17/687 ,  H03K17/693

    Abstract: Disclosed is a harmonic cancellation circuit for an RF switch branch having a first transistor with a first gate terminal and a first body terminal, a second transistor having a second gate terminal coupled to the first body terminal, and having a second body terminal coupled to the first gate terminal. Also included is a first resistor coupled between a first coupling node and the second body terminal, and a second resistor coupled between a second coupling node and the first body terminal, wherein the first transistor and second transistor are adapted to generate an inverse phase third harmonic signal relative to a third harmonic signal generated by the RF switch branch, such that the inverse phase third harmonic signal is output through the first resistor and the second resistor to the RF switch branch to reduce the third harmonic signal.

    Abstract translation: 公开了一种用于RF开关分支的谐波消除电路，具有具有第一栅极端子和第一主体端子的第一晶体管，第二晶体管具有耦合到第一主体端子的第二栅极端子，并且具有耦合到第一主体端子的第二主体端子 第一门终端。 还包括耦合在第一耦合节点和第二主体端子之间的第一电阻器和耦合在第二耦合节点和第一主体端子之间的第二电阻器，其中第一晶体管和第二晶体管适于产生反相三次谐波 信号相对于由RF开关分支产生的三次谐波信号，使得反相三次谐波信号通过第一电阻器和第二电阻器输出到RF开关分支以减少三次谐波信号。

    SERIAL BUS BUFFER WITH NOISE REDUCTION
    10.
    发明申请
    SERIAL BUS BUFFER WITH NOISE REDUCTION 有权
    串行总线缓冲器与噪声减少

    公开(公告)号：US20140304442A1

    公开(公告)日：2014-10-09

    申请号：US14160900

    申请日：2014-01-22

    Applicant: RF Micro Devices, Inc.

    Inventor： Alexander Wayne Hietala ,  Christopher Truong Ngo ,  Eric K. Bolton

    IPC: G06F13/42

    CPC classification number: G06F13/4291 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Disclosed is a digital communication control system having a serial bus buffer that includes a primary interface adapted to support serial communication over a primary bus, a buffered interface adapted to support serial communication over a buffered bus, and a controller coupled between the primary bus and the buffered bus. The primary bus is coupled to a first device and at least one second device and the buffered bus is coupled to at least one third device. The controller is adapted to receive a first data signal and a clock signal at the primary interface and replicate the first data signal and the clock signal at the buffered interface.

    Abstract translation: 公开了一种具有串行总线缓冲器的数字通信控制系统，该串行总线缓冲器包括适于支持通过主总线的串行通信的主接口，适于支持通过缓冲总线的串行通信的缓冲接口以及耦合在主总线与 缓冲总线。 主总线耦合到第一设备和至少一个第二设备，并且缓冲总线耦合到至少一个第三设备。 控制器适于在主接口处接收第一数据信号和时钟信号，并在缓冲接口处复制第一数据信号和时钟信号。

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