Reduced area schmitt trigger circuit
    21.
    发明授权
    Reduced area schmitt trigger circuit 有权
    减少面积施密特触发电路

    公开(公告)号:US08476948B2

    公开(公告)日:2013-07-02

    申请号:US12614047

    申请日:2009-11-06

    Applicant: Rajeev Jain

    Inventor: Rajeev Jain

    CPC classification number: H03K3/3565

    Abstract: A Schmitt trigger circuit includes a first inverter having an input coupled to an input terminal; a second inverter having an input coupled to the input terminal; a first transistor having a source coupled to VDD, a drain coupled to an output of the first inverter, and a gate coupled to an output terminal; a second transistor having a source coupled to ground, a drain coupled to an output of the second inverter, and a gate coupled to the output terminal; a third transistor having a source coupled to VDD, a drain coupled to the output terminal, and a gate coupled to the output of the first inverter; and a fourth transistor having a source coupled to ground, a drain coupled to the output terminal, and a gate coupled to the output of the second inverter.

    Abstract translation: 施密特触发电路包括具有耦合到输入端的输入的第一反相器; 第二反相器,其具有耦合到所述输入端子的输入; 具有耦合到VDD的源极的第一晶体管,耦合到第一反相器的输出端的漏极和耦合到输出端子的栅极; 第二晶体管,其具有耦合到地的源极,耦合到第二反相器的输出的漏极和耦合到输出端子的栅极; 具有耦合到VDD的源极的第三晶体管,耦合到输出端子的漏极和耦合到第一反相器的输出端的栅极; 以及第四晶体管,其具有耦合到地的源极,耦合到输出端子的漏极和耦合到第二反相器的输出端的栅极。

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