公开(公告)号：US20180052194A1

公开(公告)日：2018-02-22

申请号：US15699874

申请日：2017-09-08

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Jaeha Kim ,  Brian Liebowitz

IPC: G01R29/26 ,  G01R31/317

CPC classification number: G01R29/26 ,  G01R31/31709 ,  G01R31/31725

Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

公开(公告)号：US09791492B2

公开(公告)日：2017-10-17

申请号：US15209494

申请日：2016-07-13

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Jaeha Kim ,  Brian Liebowitz

IPC: H04L7/00 ,  G01R29/26 ,  G01R31/317

CPC classification number: G01R29/26 ,  G01R31/31709 ,  G01R31/31725

Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

公开(公告)号：US09660844B2

公开(公告)日：2017-05-23

申请号：US14938163

申请日：2015-11-11

Applicant: Rambus Inc.

Inventor： Brian Leibowitz ,  Jaeha Kim

IPC: H04L25/03 ,  H03M1/36 ,  H03M1/12 ,  H03M1/00

CPC classification number: H04L25/03057 ,  H03M1/004 ,  H03M1/123 ,  H03M1/1245 ,  H03M1/362 ,  H04L25/03146 ,  H04L25/03885 ,  H04L2025/03363 ,  H04L2025/03369

Abstract: A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

公开(公告)号：US20170052221A1

公开(公告)日：2017-02-23

申请号：US15209494

申请日：2016-07-13

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Jaeha Kim ,  Brian Liebowitz

IPC: G01R29/26 ,  G01R31/317

CPC classification number: G01R29/26 ,  G01R31/31709 ,  G01R31/31725

Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

Abstract translation: 能够进行片上抖动容限测量的集成电路包括：抖动发生器电路，用于产生被注入到至少一个时钟信号中的受控量的抖动;以及接收电路，用于根据至少一个时钟信号对输入信号进行采样 。 从接收器输出的采样数据值用于评估集成电路的抖动容限。