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公开(公告)号：US20200052873A1
公开(公告)日：2020-02-13
申请号：US16549303
申请日：2019-08-23
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
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公开(公告)号：US20210318371A1
公开(公告)日：2021-10-14
申请号：US17241660
申请日：2021-04-27
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Jaeha Kim , Brian Leibowitz
IPC: G01R29/26 , G01R31/317
Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
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公开(公告)号：US10887076B2
公开(公告)日：2021-01-05
申请号：US16549303
申请日：2019-08-23
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
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公开(公告)号：US20170099132A1
公开(公告)日：2017-04-06
申请号：US15209529
申请日：2016-07-13
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
CPC classification number: H04L7/0016 , G06Q10/06312 , G06Q10/103 , H04L7/0004 , H04L7/0062 , H04L7/033 , H04L7/0331 , H04L7/0334 , H04L25/062 , H04L2025/0349 , H04L2027/004 , H04L2027/0067 , H04L2027/0069
Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
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5.发明授权Methods and systems for transmitting data by modulating transmitter filter coefficients 有权通过调制发射机滤波器系数传输数据的方法和系统公开(公告)号：US09491011B2
公开(公告)日：2016-11-08
申请号：US14448006
申请日：2014-07-31
Applicant: Rambus Inc.
Inventor： Jaeha Kim , Haechang Lee , Jung-Hoon Chun , Jared Zerbe
CPC classification number: H04L25/03343 , H04B1/126 , H04L5/04 , H04L2025/03356 , H04L2025/03477 , H04L2025/03802
Abstract: A signaling system supports main and auxiliary communication channels between integrated circuits in the same direction over a single link. An equalizing transmitter applies appropriate filter coefficients to minimize the impact of intersymbol interference when transmitting the main data over a communication channel. The transmitter modulates at least one of the filter coefficients with the auxiliary data to induce apparent ISI in the transmitted signal. A main receiver ignores the apparent ISI to recover the main data, while an auxiliary receiver detects and demodulates the apparent ISI to recover the auxiliary data. The auxiliary data may be encoded using spread-spectrum techniques to reduce the impact of the auxiliary data on the main data.
Abstract translation: 信号系统通过单个链路在相同方向上支持集成电路之间的主要和辅助通信信道。 均衡发射机在通过通信信道发送主数据时，应用适当的滤波器系数来最小化符号间干扰的影响。 发射机利用辅助数据调制至少一个滤波器系数，以在发射信号中引起明显的ISI。 主接收机忽略明显的ISI以恢复主数据，而辅助接收机检测并解调明显的ISI以恢复辅助数据。 可以使用扩频技术对辅助数据进行编码，以减少辅助数据对主数据的影响。
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Patent Agency Ranking
6.发明申请Methods and Systems for Transmitting Data by Modulating Transmitter Filter Coefficients 有权通过调制发射机滤波器系数传输数据的方法和系统公开(公告)号：US20150207651A1
公开(公告)日：2015-07-23
申请号：US14448006
申请日：2014-07-31
Applicant: Rambus Inc.
Inventor： Jaeha Kim , Haechang Lee , Jung-Hoon Chun , Jared Zerbe
CPC classification number: H04L25/03343 , H04B1/126 , H04L5/04 , H04L2025/03356 , H04L2025/03477 , H04L2025/03802
Abstract: A signaling system supports main and auxiliary communication channels between integrated circuits in the same direction over a single link. An equalizing transmitter applies appropriate filter coefficients to minimize the impact of intersymbol interference when transmitting the main data over a communication channel. The transmitter modulates at least one of the filter coefficients with the auxiliary data to induce apparent ISI in the transmitted signal. A main receiver ignores the apparent ISI to recover the main data, while an auxiliary receiver detects and demodulates the apparent ISI to recover the auxiliary data. The auxiliary data may be encoded using spread-spectrum techniques to reduce the impact of the auxiliary data on the main data.
Abstract translation: 信号系统通过单个链路在相同方向上支持集成电路之间的主要和辅助通信信道。 均衡发射机在通过通信信道发送主数据时，应用适当的滤波器系数来最小化符号间干扰的影响。 发射机利用辅助数据调制至少一个滤波器系数，以在发射信号中引起明显的ISI。 主接收机忽略明显的ISI以恢复主数据，而辅助接收机检测并解调明显的ISI以恢复辅助数据。 可以使用扩频技术对辅助数据进行编码，以减少辅助数据对主数据的影响。
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公开(公告)号：US11525854B2
公开(公告)日：2022-12-13
申请号：US17241660
申请日：2021-04-27
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Jaeha Kim , Brian Leibowitz
IPC: G01R23/00 , G01R29/26 , G01R31/317
Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
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公开(公告)号：US11277254B2
公开(公告)日：2022-03-15
申请号：US17114348
申请日：2020-12-07
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
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公开(公告)号：US20200014565A1
公开(公告)日：2020-01-09
申请号：US16509148
申请日：2019-07-11
Applicant: Rambus Inc.
Inventor： Brian S. Leibowitz , Jaeha Kim
Abstract: A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE, then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.
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公开(公告)号：US10397028B2
公开(公告)日：2019-08-27
申请号：US15499310
申请日：2017-04-27
Applicant: Rambus, Inc.
Inventor： Brian S. Leibowitz , Jaeha Kim
Abstract: A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.
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