公开(公告)号：US20220165727A1

公开(公告)日：2022-05-26

申请号：US17517920

申请日：2021-11-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryota KURODA ,  Hitoshi MATSUURA

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/739 ,  H01L29/66

Abstract: A built-in resistor electrically connecting a trench gate electrode and a gate pad is formed of a conductive film formed on a semiconductor substrate via an insulating film. Here, a film thickness of the insulating film is larger than a film thickness of an insulating film in a trench and is smaller than an insulating film which is a field oxide film.

公开(公告)号：US20180350910A1

公开(公告)日：2018-12-06

申请号：US15971139

申请日：2018-05-04

Applicant: Renesas Electronics Corporation

Inventor： Shigeaki SAITO ,  Yoshito NAKAZAWA ,  Hitoshi MATSUURA ,  Yukio TAKAHASHI

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/739

CPC classification number: H01L29/0696 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/7397

Abstract: The reliability of a semiconductor device is improved. A contact trench for coupling a field plate and a field limiting ring situated at the corner part of a semiconductor device is formed of a first straight line part and a second straight line part arranged line symmetrically with respect to the crystal orientation . Respective one ends of the first straight line part and the second straight line part are coupled at the crystal orientation , and the first straight line part and the second straight line part are set to extend in different directions from the crystal orientation and the crystal orientation .

公开(公告)号：US20180190806A1

公开(公告)日：2018-07-05

申请号：US15906889

申请日：2018-02-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/66348

Abstract: To achieve a semiconductor device equipped with a low ON voltage and high load short circuit withstand trench gate IGBT. A collector region on a back surface of a semiconductor substrate is comprised of a relatively lightly-doped P+ type first collector region and a relatively heavily-doped P++ type second collector region. The P++ type second collector region includes, in plan view, interfaces between a first trench having therein a first linear trench gate electrode and an N+ type emitter region formed on the side surface of the first trench and between a second trench having therein a second linear trench gate electrode and an N+ type emitter region formed on the side surface of the second trench. This enables electrons injected from the surface side of the semiconductor substrate to reach the P++ type second collector region and offset, with them, holes injected from the back surface side of the semiconductor substrate.

公开(公告)号：US20180069110A1

公开(公告)日：2018-03-08

申请号：US15812862

申请日：2017-11-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/06

CPC classification number: H01L29/7397 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/66348

Abstract: A semiconductor device including an IGBT element having features of a low on-state voltage and a low turn-off loss is provided. The semiconductor device is comprised of a trench gate type IGBT element. The IGBT element includes: a plurality of gate trench electrodes to which gate potential is given; and a plurality of emitter trench electrodes to which emitter potential is given. Between adjacent trench electrodes, a contact to an emitter electrode layer is formed. In this regard, there is formed, in the semiconductor substrate, a P type floating region which is in contact with bottom portions of at least some of the emitter trench electrodes via an interlayer insulation layer.

公开(公告)号：US20180069108A1

公开(公告)日：2018-03-08

申请号：US15807975

申请日：2017-11-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7397 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/66348

Abstract: In an equal width active cell IE type IGBT, a wide active cell IE type IGBT, and the like, an active cell region is equal in trench width to an inactive cell region, or the trench width of the inactive cell region is narrower. Accordingly, it is relatively easy to ensure the breakdown voltage. However, with such a structure, an attempt to enhance the IE effect entails problems such as further complication of the structure. The present invention provides a narrow active cell IE type IGBT having an active cell two-dimensional thinned-out structure, and not having a substrate trench for contact.

公开(公告)号：US20170365697A1

公开(公告)日：2017-12-21

申请号：US15694679

申请日：2017-09-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/10 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7397 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4238

Abstract: The performance of a semiconductor device is improved. An emitter electrode is coupled to a P-type body region and an N+-type emitter region of a linear active cell region via a contact groove formed on an interlayer insulating film and is coupled to a P-type body region of a linear hole connector cell region via a contact groove. The contact grooves arranged in the linear hole connector cell region are shorter than the contact groove in plan view.

公开(公告)号：US20170062336A1

公开(公告)日：2017-03-02

申请号：US15242788

申请日：2016-08-22

Applicant: Renesas Electronics Corporation

Inventor： Yukio TAKAHASHI ,  Hitoshi MATSUURA

IPC: H01L23/525 ,  H01L29/739 ,  H01L27/02 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L23/5258 ,  H01L22/22 ,  H01L23/5228 ,  H01L27/0255 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/0619 ,  H01L29/402 ,  H01L29/66348 ,  H01L29/7397

Abstract: A semiconductor device includes: a semiconductor substrate having a main surface; a first insulating film formed in a convex shape and provided on the main surface of the semiconductor substrate; a first diffusion layer formed on the semiconductor substrate and provided to surround the first insulating film formed in a convex shape, the first diffusion layer being different in conductivity type from the semiconductor substrate; a first conductive layer formed so as to extend across the first insulating film formed in a convex shape, the first conductive layer forming a fuse element; and a second insulating film provided on the first conductive layer.

Abstract translation: 半导体器件包括：具有主表面的半导体衬底; 形成为凸形并设置在所述半导体衬底的主表面上的第一绝缘膜; 第一扩散层，其形成在所述半导体基板上，并且设置成围绕形成为凸状的所述第一绝缘膜，所述第一扩散层的导电类型与所述半导体基板不同; 第一导电层，其形成为跨越形成为凸形的第一绝缘膜延伸，所述第一导电层形成熔丝元件; 以及设置在第一导电层上的第二绝缘膜。

公开(公告)号：US20240162335A1

公开(公告)日：2024-05-16

申请号：US18452811

申请日：2023-08-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryota KURODA ,  Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/0696 ,  H01L29/66348

Abstract: A semiconductor device includes a trench formed in an element formation region of a semiconductor substrate, an insulating film formed on an inner wall of the trench, a p-type semiconductor portion embedded in a part of the trench via the insulating film, and an n-type semiconductor portion embedded in another part of the trench via the insulating film and provided so as to contact with the p-type semiconductor portion.

公开(公告)号：US20190006496A1

公开(公告)日：2019-01-03

申请号：US15980635

申请日：2018-05-15

Applicant: Renesas Electronics Corporation

Inventor： Ryo KANDA ,  Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/10 ,  H01L29/08

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having an upper surface, a trench electrode placed inside a trench formed on the upper surface, and a trench insulating film placed between the trench electrode and the semiconductor substrate, and the semiconductor substrate includes a drift layer, a floating layer for electric field reduction, a hole barrier layer, a body layer and an emitter layer, and the emitter layer, the body layer and the hole barrier layer are separated from the drift layer by the floating layer for electric field reduction, and a path of a carrier passing through an inverted layer formed in the body layer includes the body layer, the hole barrier layer, a non-inverted region of the floating layer for electric field reduction, and the drift layer.

公开(公告)号：US20180047838A1

公开(公告)日：2018-02-15

申请号：US15798209

申请日：2017-10-30

Applicant: Renesas Electronics Corporation

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7397 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/66325

Abstract: A linear active cell region is formed from a plurality of divided active cell regions arranged apart from each other in a second direction (y direction). The linear hole collector cell region is formed from a plurality of divided hole collector cell regions arranged apart from each other in the second direction (y direction). A P-type floating region is formed in a semiconductor substrate between the linear active cell region and the linear hole collector cell region adjacent to each other in a first direction (x direction), between the divided active cell regions adjacent to each other in the second direction (y direction), and between the divided hole collector cell regions adjacent to each other in the second direction (y direction).