利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

18 条记录 (耗时 0.02 秒)

    TRENCH GATE IGBT
    1.
    发明申请
    TRENCH GATE IGBT 审中-公开

    公开(公告)号：US20180182875A1

    公开(公告)日：2018-06-28

    申请号：US15798218

    申请日：2017-10-30

    申请人： Renesas Electronics Corporation

    发明人： Ryo KANDA ,  Hitoshi MATSUURA ,  Shuichi KIKUCHI

    IPC分类号： H01L29/739

    CPC分类号： H01L29/7397 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/407 ,  H01L29/4238

    摘要： A high-performance trench gate IGBT is provided. A trench gate IGBT according to one embodiment includes: a semiconductor substrate (11); a channel layer (15) provided on the semiconductor substrate (11); two floating P-type layer (12) provided on both sides of the channel layer 15, the floating P-type layers (12) being deeper than the channel layer (15); two emitter trenches (13) disposed between the two floating P-type layers (12), the emitter trenches (13) being respectively in contact with the floating P-type layers (12); at least two gate trenches (14) disposed between the two emitter trenches (13); and a source diffusion layer (19) disposed between the two gate trenches 14, the source diffusion layer (19) being in contact with each of the gate trenches (14).

    Semiconductor Device
    2.
    发明申请
    Semiconductor Device 有权
    半导体器件

    公开(公告)号：US20150115342A1

    公开(公告)日：2015-04-30

    申请号：US14517657

    申请日：2014-10-17

    申请人： Renesas Electronics Corporation

    发明人： Yoshinori KAYA ,  Yasushi NAKAHARA ,  Azuma ARAYA ,  Ryo KANDA ,  Tomonobu KURIHARA ,  Tetsu TODA

    IPC分类号： H01L27/06 ,  H01L29/06

    CPC分类号： H02M1/088 ,  H01L27/0285 ,  H01L27/0292 ,  H01L27/0296 ,  H01L27/0629 ,  H01L27/0922 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1079 ,  H01L29/405 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7838 ,  H03K2017/6875 ,  H03K2217/0081

    摘要： Provided is a semiconductor device including a substrate of a first conductivity type, a first circuit region, a separation region, a second circuit region, and a rectifying element. The rectifying element has a second conductivity type layer, a first high concentration second conductivity type region, a second high concentration second conductivity type region, an element isolation film, a first insulation layer, and a first conductive film. A first contact is coupled to the first high concentration second conductivity type region, and a second contact is coupled to the second high concentration second conductivity type region. A third contact is coupled to the first conductive film. The first contact, the second contact and the third contact are separated from each other.

    摘要翻译： 提供了包括第一导电类型的衬底，第一电路区域，分离区域，第二电路区域和整流元件的半导体器件。 整流元件具有第二导电类型层，第一高浓度第二导电类型区域，第二高浓度第二导电类型区域，元件隔离膜，第一绝缘层和第一导电膜。 第一触点耦合到第一高浓度第二导电类型区域，第二触点耦合到第二高浓度第二导电类型区域。 第三触点耦合到第一导电膜。 第一触点，第二触点和第三触点彼此分离。

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190035745A1

    公开(公告)日：2019-01-31

    申请号：US16151585

    申请日：2018-10-04

    申请人： Renesas Electronics Corporation

    发明人： Kuniharu MUTO ,  Ryo KANDA

    IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/495 ,  H01L23/544 ,  H02M7/5387 ,  H02M7/00 ,  H02P27/06 ,  H02M1/00

    摘要： A semiconductor device includes a first and second semiconductor chips, a resistive component, and a semiconductor chip including a first circuit coupled to electrodes on both ends of the resistive component. A sealing body has a first long side, a second side, a third short side, and a fourth short side. In a Y-direction, each of the first and second semiconductor chips is disposed at a position closer to the first side than to the second side, while the semiconductor chip is disposed at a position closer to the second side than to the first side. Also, in the Y-direction, the resistive component, the second semiconductor chips, and the first semiconductor chips are arranged in order of increasing distance from the third side toward the fourth side, while the semiconductor chip is disposed at a position closer to the third side than to the fourth side.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20180358438A1

    公开(公告)日：2018-12-13

    申请号：US15955819

    申请日：2018-04-18

    申请人： Renesas Electronics Corporation

    发明人： Ryo KANDA

    IPC分类号： H01L29/08 ,  H01L29/43 ,  H01L29/423 ,  H01L21/02

    CPC分类号： H01L27/0623 ,  H01L21/02164 ,  H01L29/0804 ,  H01L29/42304 ,  H01L29/4232 ,  H01L29/435 ,  H01L29/66325 ,  H01L29/7393 ,  H01L29/7397 ,  H01L2924/13055

    摘要： According to one embodiment, a semiconductor device includes a semiconductor substrate, a trench electrode provided in a trench, a trench insulating film provided between the trench electrode and the semiconductor substrate, a MOS electrode provided near the trench electrode, and a MOS insulating film provided between the MOS electrode and the semiconductor substrate, in which the semiconductor substrate includes a first semiconductor layer, a second semiconductor layer provided over the first semiconductor layer, a third semiconductor layer provided over the second semiconductor layer, a fourth semiconductor layer provided below the MOS electrode, and one and the other of fifth semiconductor layers provided on both sides of the fourth semiconductor layer, and in which the semiconductor device further includes a wiring layer that couples the one of the fifth semiconductor layers and the second semiconductor layer together.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20180358437A1

    公开(公告)日：2018-12-13

    申请号：US15934896

    申请日：2018-03-23

    申请人： Renesas Electronics Corporation

    发明人： Ryo KANDA

    IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/739

    CPC分类号： H01L29/0696 ,  H01L29/1095 ,  H01L29/66348 ,  H01L29/7396

    摘要： According to an embodiment, a semiconductor device 1 includes a semiconductor substrate 50 including an upper surface, a trench electrode 22 provided inside a trench 20 formed on the upper surface, and a trench insulating film 21 provided between the trench electrode 22 and the semiconductor substrate 50. The semiconductor substrate 50 includes a first semiconductor layer of a first conductivity type, a lower end of the trench electrode 22 reaching the first semiconductor layer, a deep layer 19 of a second conductivity type partially provided on the first semiconductor layer in contact with the trench insulating film 21, a second semiconductor layer of the second conductivity type provided on the first semiconductor layer and on the deep layer 19 in contact with the trench insulating film 21, and a third semiconductor layer of the first conductivity type provided on the second semiconductor layer above the deep layer 19.

    SEMICONDUCTOR DEVICE
    10.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150262990A1

    公开(公告)日：2015-09-17

    申请号：US14714111

    申请日：2015-05-15

    申请人： Renesas Electronics Corporation

    发明人： Ryo KANDA ,  Tetsu TODA ,  Yasushi NAKAHARA ,  Yoshinori KAYA

    IPC分类号： H01L27/02 ,  H01L29/40 ,  H01L29/06 ,  H01L29/78

    CPC分类号： H01L27/0207 ,  H01L21/761 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

    摘要： A field plate electrode is repetitively disposed in a folded manner or a spiral shape in a direction along an edge of a first circuit region. A coupling transistor couples a first circuit to a second circuit lower in supply voltage than the first circuit. A second conductivity type region is disposed around the coupling transistor. A part of the field plate electrode partially overlaps with the second conductivity type region. The field plate electrode is electrically coupled to a drain electrode of the coupling transistor at a portion located on the first circuit region side from a center thereof in a width direction of the separation region. A ground potential or a power potential of the second circuit is applied to the field plate electrode at a portion located on the second conductivity type region side from the center.

    摘要翻译： 场板电极在沿着第一电路区域的边缘的方向上以折叠方式或螺旋形状重复地布置。 耦合晶体管将第一电路耦合到电源电压低于第一电路的第二电路。 第二导电类型区域设置在耦合晶体管周围。 场板电极的一部分与第二导电类型区域部分重叠。 场平板电极在分离区域的宽度方向上的位于第一电路区域侧的部分的电极上耦合到耦合晶体管的漏电极。 第二电路的接地电位或功率电位在距中心的第二导电类型区域侧的部分施加到场板电极。