公开(公告)号：US20110215860A1

公开(公告)日：2011-09-08

申请号：US13007483

申请日：2011-01-14

Applicant: Carlos Mazure ,  Richard Ferrant

Inventor： Carlos Mazure ,  Richard Ferrant

IPC: G05F1/10 ,  H01L27/105 ,  G06F17/50

CPC classification number: H01L27/1203 ,  H01L29/78609 ,  H01L29/78648

Abstract: The invention provides a data-path cell specifically adapted to its environment for use in an integrated circuit produced on a semiconductor-on-insulator (SeOI) substrate. The data-path cell includes an array of field-effect transistors, each transistor having a source region, a drain region and a channel region formed in the thin semiconductor layer of the SeOI substrate, and further having a front gate control region formed above the channel region. In particular, one or more transistors of the data-path cell further includes a back gate control region formed in the bulk substrate beneath the channel region and configured so as to modify the performance characteristics of the transistor in dependence on its state of bias. Also, an integrated circuit including one or more of the data-path cells and methods for designing or driving these data-path cells.

Abstract translation: 本发明提供一种特别适用于其环境的数据通道单元，用于在绝缘体上半导体（SeOI）衬底上制造的集成电路中。 数据通道单元包括场效应晶体管阵列，每个晶体管具有形成在SeOI衬底的薄半导体层中的源极区，漏极区和沟道区，并且还具有形成在栅极上的前栅极控制区 渠道区域。 特别地，数据通道单元的一个或多个晶体管还包括形成在沟道区下面的体衬底中的背栅极控制区域，并且被配置为根据其偏置状态来修改晶体管的性能特性。 而且，包括一个或多个数据路径单元的集成电路以及用于设计或驱动这些数据路径单元的方法。

公开(公告)号：US20110169090A1

公开(公告)日：2011-07-14

申请号：US12984466

申请日：2011-01-04

Applicant: Carlos Mazure ,  Richard Ferrant

Inventor： Carlos Mazure ,  Richard Ferrant

IPC: H01L27/12 ,  H01L21/36 ,  H01L21/76

CPC classification number: H01L27/1203 ,  H01L21/743 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10873 ,  H01L29/732 ,  H01L29/7841 ,  H01L29/78639

Abstract: The invention relates to a semiconductor device produced on a semiconductor-on-insulator substrate that includes a thin layer of semiconductor material separated from a base substrate by a buried insulating layer, the device including a first conducting region in the thin layer, a second conducting region in the base substrate and a contact connecting the first region to the second region through the insulating layer. The invention also relates to a process for fabricating such semiconductor devices.

Abstract translation: 本发明涉及一种在绝缘体上半导体衬底上制造的半导体器件，其包括通过掩埋绝缘层与基底衬底分离的半导体材料的薄层，该器件包括薄层中的第一导电区域，第二导电层 区域和通过绝缘层将第一区域连接到第二区域的接触。 本发明还涉及制造这种半导体器件的方法。

公开(公告)号：US20100002501A1

公开(公告)日：2010-01-07

申请号：US12168671

申请日：2008-07-07

Applicant: Rainer Leuschner ,  Ulrich Klostermann ,  Richard Ferrant

Inventor： Rainer Leuschner ,  Ulrich Klostermann ,  Richard Ferrant

IPC: G11C11/02 ,  H01L21/00 ,  G11C7/00

CPC classification number: G11C7/04 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/16 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/307 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: A thermally-assisted MRAM structure which is programmable at a writing mode operating temperature is presented and includes an anti-ferromagnet, an artificial anti-ferromagnet, a barrier layer, and a free magnetic layer. The anti-ferromagnet is composed of a material having a blocking temperature Tb which is lower than the writing mode operating temperature of the magnetic random access memory structure. The artificial anti-ferromagnet is magnetically coupled to the anti-ferromagnet, and includes first and second magnetic layers, and a coupling layer interposed therebetween, the first and second magnetic layers having different Curie point temperatures. The barrier layer is positioned to be between the second magnetic layer and the free magnetic layer.

Abstract translation: 提出了一种在写入模式工作温度下可编程的热辅助MRAM结构，其包括反铁磁体，人造抗铁磁体，阻挡层和自由磁性层。 抗铁磁体由具有比磁性随机存取存储器结构的写入模式工作温度低的阻挡温度Tb的材料构成。 人造抗铁磁体磁耦合到抗铁磁体，并且包括第一和第二磁性层以及插入其间的耦合层，第一和第二磁性层具有不同的居里点温度。 阻挡层被定位在第二磁性层和自由磁性层之间。

公开(公告)号：US20070159911A1

公开(公告)日：2007-07-12

申请号：US11713284

申请日：2007-03-02

Applicant: Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

Inventor： Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

IPC: G11C8/00

CPC classification number: G11C11/404 ,  G11C7/18 ,  G11C8/08 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4097 ,  G11C2211/4016 ,  G11C2211/4065 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

Abstract translation: 这里描述和说明了许多发明。 在第一方面，本发明涉及一种从数据读取和将数据写入存储器件的存储单元的存储器件和技术。 在这方面，在本发明的这个方面的一个实施例中，用于操作该装置的存储器件和技术使得最小化，减少和/或消除电荷泵送现象的衰弱影响。 本发明的该实施例采用最小化，减少和/或消除幅度和/或极性的转变的控制信号。 在另一个实施例中，本发明是一种包括存储阵列的半导体存储器件，该存储器阵列包括以行和列的矩阵排列的多个半导体动态随机存取存储器单元。 每个半导体动态随机存取存储单元包括晶体管，其具有源极区，漏极区，设置在源极区和漏极区之间且与源极区和漏极区相邻的电浮动体区域，以及与该区域和漏极区域间隔开并电容耦合的栅极 身体区域。 每个晶体管包括代表身体区域中的第一电荷的第一状态和代表身体区域中的第二电荷的第二数据状态。 此外，每排半导体动态随机存取存储器单元包括仅与相关行的半导体动态随机存取存储单元连接的相关联的源极线。

公开(公告)号：US07212432B2

公开(公告)日：2007-05-01

申请号：US10955837

申请日：2004-09-30

Applicant: Richard Ferrant ,  Daniel Braun

Inventor： Richard Ferrant ,  Daniel Braun

IPC: G11C11/00

CPC classification number: H01L27/228 ,  G11C8/14 ,  G11C11/15 ,  G11C2213/79 ,  H01L29/785

Abstract: A resistive memory cell random access memory device and method for fabrication. In one embodiment, the invention relates to a resistive memory cell random access memory device comprising a plurality of first current lines; a plurality of second current lines; a plurality of third current lines being formed as split current lines; and an array of resistive memory cells arranged in columns defined by said first current lines and rows defined by said third current lines, each resistive memory cell including a resistive memory element and an access transistor connected in series, each memory cell being connected between one of said first current lines and a reference potential, wherein said access transistors being FinFET-type field effect transistors, each one having two independent gates and a common floating body, and wherein each third current line being connected to one of said two independent gates of each one of the access transistors of a row of said array and being connected to one of said two independent gates of each one of the access transistors of an adjacent row of said array. It also relates to a method for its fabrication.

Abstract translation: 一种电阻式存储单元随机存取存储器件及其制造方法。 在一个实施例中，本发明涉及包括多条第一电流线的电阻式存储单元随机存取存储器件; 多条第二电流线; 多条第三电流线被形成为分流电流线; 以及由所述第一电流线限定的列和由所述第三电流线限定的行的电阻性存储单元的阵列，每个电阻性存储单元包括电阻性存储元件和串联连接的存取晶体管，每个存储单元连接在 所述第一电流线和参考电位，其中所述存取晶体管是FinFET型场效应晶体管，每个具有两个独立的栅极和共同的浮动体，并且其中每个第三电流线连接到每个的所述两个独立栅极之一 所述阵列的行的存取晶体管之一并且连接到所述阵列的相邻行的每个存取晶体管的每一个的所述两个独立栅极之一。 它还涉及其制造方法。

公开(公告)号：US07187581B2

公开(公告)日：2007-03-06

申请号：US11079590

申请日：2005-03-14

Applicant: Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

Inventor： Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

IPC: G11C11/34 ,  G11C7/00

CPC classification number: G11C11/404 ,  G11C7/18 ,  G11C8/08 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4097 ,  G11C2211/4016 ,  G11C2211/4065 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

公开(公告)号：US07161863B2

公开(公告)日：2007-01-09

申请号：US10627955

申请日：2003-07-25

Applicant: Richard Ferrant ,  François Jacquet

Inventor： Richard Ferrant ,  François Jacquet

IPC: G11C7/00

CPC classification number: G11C11/406

Abstract: A DRAM including an array of storage elements arranged in lines and columns, and for each column: write means adapted to biasing at least a selected one of the elements to a charge level chosen from among a first predetermined high level and a second predetermined low level, combined with read circuitry adapted to determining whether the stored charge level is greater or smaller than a predetermined charge level; and isolation circuitry adapted to isolating the array from the read and/or write means, each column further including refreshment means, distinct from the read and write circuit, for increasing, beyond the first and second predetermined levels, the charge stored in a storage element.

Abstract translation: 一种DRAM，包括排列成行和列的存储元件的阵列，并且用于每列：写入装置，其适于将至少一个所选元素偏置到从第一预定高电平和第二预定低电平中选择的电荷电平 与读取电路组合，适于确定所存储的电荷电平是否大于或小于预定电荷电平; 以及隔离电路，其适于将阵列与读取和/或写入装置隔离，每列还包括与读取和写入电路不同的刷新装置，用于在第一和第二预定级别之外增加存储在存储元件中的电荷 。

公开(公告)号：US06765405B2

公开(公告)日：2004-07-20

申请号：US10191089

申请日：2002-07-09

Applicant: Jean-Francois Hugues ,  Philippe Roche ,  Richard Ferrant

Inventor： Jean-Francois Hugues ,  Philippe Roche ,  Richard Ferrant

IPC: H03K1716

CPC classification number: H03K19/00338 ,  H03K19/0075

Abstract: Disclosed are protection circuitry, and methods of operating the same, for use with clock circuits associated with integrated circuits (ICs). According to one exemplary embodiment, the protection circuitry is operable to generate at least two intermediate clock signals as a function of a received clock signal, and process the at least two intermediate clock signals to (i) cause an output of the protection circuitry to enter a high-impedance state when the at least two intermediate clock signals are different, and (ii) generate a resultant clock signal at the output of the protection circuitry equal to the received clock signal when the at least two intermediate clock signals are identical.

Abstract translation: 公开了用于与集成电路（IC）相关的时钟电路使用的保护电路及其操作方法。 根据一个示例性实施例，保护电路可操作以产生作为接收到的时钟信号的函数的至少两个中间时钟信号，并处理该至少两个中间时钟信号以使（i）使保护电路的输出进入 当所述至少两个中间时钟信号不同时，高阻抗状态;以及（ii）当所述至少两个中间时钟信号相同时，在所述保护电路的输出处产生等于接收到的时钟信号的合成时钟信号。

公开(公告)号：US06556092B1

公开(公告)日：2003-04-29

申请号：US09627814

申请日：2000-07-28

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: H03B532

CPC classification number: H03K3/012 ,  H03K3/0307

Abstract: A low consumption oscillator having an inverter connected to a high supply potential and to a low supply potential via two respective resistors, with the resistors formed of capacitors having strong leakages.

Abstract translation: 低功耗振荡器，其具有通过两个相应的电阻器连接到高电源电位和低电源电压的反相器，电阻器由具有强泄漏的电容器形成。

公开(公告)号：US4761767A

公开(公告)日：1988-08-02

申请号：US818030

申请日：1986-01-13

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC classification number: G11C29/785 ,  G11C29/832

Abstract: The invention provides integrated circuit memories with repair circuits. These repair circuits allow redundant memory cell lines to be substituted for defective cell lines. The invention takes advantage of the existence of these substitution circuits for electrically, and no longer only functionally, decoupling the defective lines. A connection connects circuits for biasing the cell lines to the repair circuit of this line. When the line is repaired (i.e. neutralized) it is automatically unbiased.

Abstract translation: 本发明提供具有修复电路的集成电路存储器。 这些修复电路允许冗余存储器单元线代替有缺陷的细胞系。 本发明利用这些替代电路的存在，这些替代电路用于电而且不再仅在功能上解耦有缺陷的线。 一个连接连接用于将电池线偏置到该线路的修复电路的电路。 当线路被修复（即被中和）时，它是自动无偏的。