利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

62 条记录 (耗时 0.191 秒)

    Programmable logic device with enhanced multiplexing capabilities in interconnect resources
    21.
    发明授权
    Programmable logic device with enhanced multiplexing capabilities in interconnect resources 有权
    具有增强的互连资源复用能力的可编程逻辑器件

    公开(公告)号：US06278288B1

    公开(公告)日：2001-08-21

    申请号：US09574371

    申请日：2000-05-19

    申请人： Andy L. Lee ,  Richard G. Cliff ,  David Jefferson ,  Cameron McClintock ,  Kurosu R. Altaf

    发明人： Andy L. Lee ,  Richard G. Cliff ,  David Jefferson ,  Cameron McClintock ,  Kurosu R. Altaf

    IPC分类号： G06F738

    CPC分类号： H03K19/17752 ,  H03K19/1737 ,  H03K19/17736 ,  H03K19/1778

    摘要： A programmable logic integrated circuit device is provided with enhanced capability for dynamically multiplexing signals on the device. Controllable connectors that are provided on the device for connecting any of several connector input signals to a connector output are controlled by control signals that can be programmable selected to be either constant or variable signals. If a control signal is selected to be a variable signal, then the connector controlled by that control signal can be operated as a dynamic multiplexer of the input signals to that connector. The controllable connectors may advantageously be used as the connectors that are employed for allowing several possible signal sources to effectively share a smaller of number of signal drivers.

    摘要翻译： 可编程逻辑集成电路器件具有增强的功能，用于在器件上动态地复用信号。 在设备上提供的用于将多个连接器输入信号中的任何一个连接到连接器输出的可控连接器由可编程选择为恒定或可变信号的控制信号控制。 如果控制信号被选择为可变信号，则由该控制信号控制的连接器可以作为到该连接器的输入信号的动态多路复用器来操作。 可控连接器可以有利地用作连接器，其用于允许几个可能的信号源有效地共享更少数量的信号驱动器。

    Programmable logic array integrated circuits with segmented, selectively connectable, long interconnection conductors
    22.
    发明授权
    Programmable logic array integrated circuits with segmented, selectively connectable, long interconnection conductors 失效
    具有分段，可选择连接的长互连导体的可编程逻辑阵列集成电路

    公开(公告)号：US5705939A

    公开(公告)日：1998-01-06

    申请号：US730351

    申请日：1996-10-15

    申请人： Cameron McClintock ,  Richard G. Cliff ,  William Leong

    发明人： Cameron McClintock ,  Richard G. Cliff ,  William Leong

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17704

    摘要： A programmable logic array integrated circuit device has regions of programmable logic grouped in blocks disposed on the device in a two-dimensional array of intersecting rows and columns. Each block includes a relatively small number of logic regions to reduce the size and complexity of the local feedback circuity required in the block. Interconnection conductors extend along each row and column of blocks. Some of these conductors are segmented along their length to permit independent use of each segment. When longer interconnections are required, however, adjacent segments can be interconnected by programmable bi-directional switches between the segments.

    摘要翻译： 可编程逻辑阵列集成电路器件具有以可交叉行和列的二维阵列布置在器件上的块分组的可编程逻辑区域。 每个块包括相对较少数量的逻辑区域，以减小块中所需的局部反馈电路的尺寸和复杂度。 互连导体沿着块的每一行和一列延伸。 这些导体中的一些沿其长度被分段以允许独立使用每个段。 然而，当需要更长的互连时，相邻的段可以通过段之间的可编程双向开关互连。

    Programmable logic array device with grouped logic regions and three types of conductors
    23.
    发明授权
    Programmable logic array device with grouped logic regions and three types of conductors 失效
    具有分组逻辑区和三种类型导体的可编程逻辑阵列器件

    公开(公告)号：US5537057A

    公开(公告)日：1996-07-16

    申请号：US388300

    申请日：1995-02-14

    申请人： William W. Leong ,  Richard G. Cliff ,  Cameron McClintock

    发明人： William W. Leong ,  Richard G. Cliff ,  Cameron McClintock

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17744

    摘要： A programmable logic array device in which programmable logic regions are arranged in groups of four is provided. The device includes direct connect conductors for carrying signals totally within one group of four regions as well as to certain adjacent programmable logic regions, local conductors for carrying signals within groups and among adjacent groups, and global conductors for carrying device-wide signals. Connections among the various conductors, and between conductors and programmable logic regions, are provided to optimize the connection resources by avoiding switched conductor paths wherever possible.

    摘要翻译： 提供了可编程逻辑阵列器件，其中可编程逻辑区域以四个成组排列。 该装置包括用于在四个区域的一组内以及某些相邻的可编程逻辑区域中携带信号的直接连接导体，用于在组内和相邻组之间传送信号的本地导体以及用于承载设备范围信号的全局导体。 提供各种导体之间以及导体和可编程逻辑区之间的连接，以尽可能避免开关导体路径来优化连接资源。

    Redundancy circuitry for logic circuits
    25.
    发明授权
    Redundancy circuitry for logic circuits 有权
    用于逻辑电路的冗余电路

    公开(公告)号：US6091258A

    公开(公告)日：2000-07-18

    申请号：US433544

    申请日：1999-11-03

    申请人： Cameron McClintock ,  Andy L. Lee ,  Richard G. Cliff

    发明人： Cameron McClintock ,  Andy L. Lee ,  Richard G. Cliff

    IPC分类号： G06F11/20 ,  G11C29/00 ,  H03K19/177 ,  H03K19/003 ,  H03K19/173

    CPC分类号： H03K19/17764 ,  G11C29/808 ,  H03K19/17728

    摘要： Redundant circuitry for a logic circuit such as a programmable logic device is provided. The redundant circuitry allows the logic circuit to be repaired by replacing a defective logic area on the circuit with a redundant logic circuit. Rows and columns of logic areas may be logically remapped by row and column swapping. The logic circuit contains dynamic control circuitry for directing programming data to various logic areas on the circuit in an order defined by redundancy configuration data. Redundancy may be implemented using either fully or partially redundant logic areas. Logic areas may be swapped to remap a partially redundant logic area onto a logic area containing a defect. The defect may then be repaired using row or column swapping or shifting. A logic circuit containing folded rows of logic areas may be repaired by replacing a defective half-row with a redundant half-row.

    摘要翻译： 提供了诸如可编程逻辑器件之类的逻辑电路的冗余电路。 冗余电路允许通过用冗余逻辑电路替换电路上的故障逻辑区域来修复逻辑电路。 逻辑区域的行和列可以通过行和列交换逻辑地重新映射。 逻辑电路包含动态控制电路，用于以由冗余配置数据定义的顺序将编程数据引导到电路上的各种逻辑区域。 可以使用完全或部分冗余的逻辑区域实现冗余。 可以交换逻辑区域以将部分冗余的逻辑区域重新映射到包含缺陷的逻辑区域。 然后可以使用行或列交换或移位来修复缺陷。 可以通过用冗余半行代替缺陷半行来修复包含折叠行的逻辑区域的逻辑电路。

    Programmable logic array integrated circuits with segmented, selectively connectable, long interconnection conductors
    27.
    发明授权
    Programmable logic array integrated circuits with segmented, selectively connectable, long interconnection conductors 失效
    具有分段，可选择连接的长互连导体的可编程逻辑阵列集成电路

    公开(公告)号：US5614840A

    公开(公告)日：1997-03-25

    申请号：US443119

    申请日：1995-05-17

    申请人： Cameron McClintock ,  Richard G. Cliff ,  William Leong

    发明人： Cameron McClintock ,  Richard G. Cliff ,  William Leong

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/17704

    摘要： A programmable logic array integrated circuit device has regions of programmable logic grouped in blocks disposed on the device in a two-dimensional array of intersecting rows and columns. Each block includes a relatively small number of logic regions to reduce the size and complexity of the local feedback circuity required in the block. Interconnection conductors extend along each row and column of blocks. Some of these conductors are segmented along their length to permit independent use of each segment. When longer interconnections are required, however, adjacent segments can be interconnected by programmable bi-directional switches between the segments.

    摘要翻译： 可编程逻辑阵列集成电路器件具有以可交叉行和列的二维阵列布置在器件上的块分组的可编程逻辑区域。 每个块包括相对较少数量的逻辑区域，以减小块中所需的局部反馈电路的尺寸和复杂度。 互连导体沿着块的每一行和一列延伸。 这些导体中的一些沿其长度被分段以允许独立使用每个段。 然而，当需要更长的互连时，相邻的段可以通过段之间的可编程双向开关互连。

    Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks
    30.
    发明授权
    Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks 失效
    具有逻辑区块的可编程逻辑阵列集成电路分为超级块

    公开(公告)号：US06396304B2

    公开(公告)日：2002-05-28

    申请号：US09460285

    申请日：1999-12-09

    申请人： Richard G. Cliff ,  Cameron McClintock ,  William Leong

    发明人： Richard G. Cliff ,  Cameron McClintock ,  William Leong

    IPC分类号： A03K19177

    CPC分类号： H03K19/17736 ,  H03K19/04 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17796

    摘要： A programmable logic array integrated circuit device has logic regions grouped in blocks, which are in turn grouped in super-blocks. The super-blocks are disposed on the device in a two-dimensional array of intersecting rows and columns. Global conductors are associated with each row and column. Super-block feeding conductors associated with each super-block feed signals from the global conductors to any logic region in the super-block. Local feedback conductors feed back logic region output signals to all logic regions in a block. The super-block feeding conductors are also used to interconnect the logic regions in a super-block so that the global conductors do not have to be used for that purpose.

    摘要翻译： 可编程逻辑阵列集成电路器件具有以块为单位的逻辑区域，其又被分组成超块。 超级块以相交的行和列的二维阵列布置在设备上。 全局导体与每行和列相关联。 与每个超级块馈送相关联的超块馈送导体将信号从全局导体连接到超块中的任何逻辑区域。 局部反馈导体将逻辑区域输出信号反馈到块中的所有逻辑区域。 超块馈电导体还用于互连超块中的逻辑区域，使得全局导体不必用于该目的。